Integrated circuit memory with improved di/dt control

Details Integrated circuit memory with improved di/dt control Integrated circuit memory with improved di/dt control

1990-01-04

1991-02-05

Clawson, Jr., Joseph E.

Static information storage and retrieval

Read/write circuit

Precharge

36518905, 3652335, 307465, 307480, 307481, G11C 700

Patent

active

049911406

ABSTRACT:
An integrated circuit memory with improved di/dt control. The memory stores a plurality of data bits at intersections of word lines and bit line pairs. In response to a change in at least one of a plurality of address signals during a read cycle, first and second precharge signals are asserted, the second precharge signal asserted after the first precharge signal. An output buffer provides a data output signal at a voltage between a logic high and a logic low voltage in response to an assertion of the second precharge signal, and provides said data output signal corresponding to a voltage on an enabled bit line pair in response to a negation of the first precharge signal. Thus, the voltage on the data output signal changes less when the data bit is provided during the data period. The memory thus improves di/dt for a given access time, or conversely, allows reduced access time for a given di/dt.

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A 21-NS 32K.times.8 CMOS Static RAM with a Selectively Pumped P-Well Array, by Karl Wang et al, IEEE Journal of Solid State Circuits, vol. SC-22, No. 5, Oct. 1987.

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