Integrated circuit memory having a power supply independent inpu

Details Integrated circuit memory having a power supply independent inpu Integrated circuit memory having a power supply independent inpu

1995-03-13

1996-09-10

Westin, Edward P.

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Signal level or switching threshold stabilization

326 80, 326 24, 327205, 327207, H03K 19003

Patent

active

055549420

ABSTRACT:
An integrated circuit memory (114) has a power supply independent address buffer (50) that comprises an inverter (60), a bipolar transistor (67), and a P-channel transistor (68). The inverter (60) has an output terminal coupled to a base of the bipolar transistor (67). The P-channel transistor (63) is for injecting a current at the output terminal of the inverter in response to a reference voltage. The reference voltage varies proportionally to variations of a power supply voltage in order to compensate for gate-to-source voltage changes of a P-channel transistor (61) of the inverter (60) that occurs as a result of a changing power supply voltage. For address buffer (50), a range of address transition times as a function of power supply voltage is decreased, thus improving an address set-up and hold time of the integrated circuit memory (114).

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patent: 5416366 (1995-05-01), Adachi

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