Integrated circuit memory devices with latch-free page buffers t

Details Integrated circuit memory devices with latch-free page buffers t Integrated circuit memory devices with latch-free page buffers t

1996-10-15

1998-06-02

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

3652385, G11C 800

Patent

active

057611327

ABSTRACT:
Integrated circuit memory devices with latch-free page buffers therein include a page buffer for electrically coupling a bit line from an array of memory cells to a buffer output. The page buffers generate a first logic state at an output thereof when the bit line is at a first logic potential and a high-impedance logic state when the bit line is at a second logic potential, during a memory read operation. An output buffer is also provided for converting the high-impedance state and the first logic state generated by the page buffer to respective opposite logic states (e.g, logic 1 and logic 0). The bit line data is used to directly trigger the appropriate state of the page buffer output by coupling a gate of an insulated-gate isolation transistor to the bit line data and then reading the source of the isolation transistor as the page buffer output.

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