Integrated circuit memory devices with improved layout of fuse b

Details Integrated circuit memory devices with improved layout of fuse b Integrated circuit memory devices with improved layout of fuse b

1998-11-25

2000-07-25

Yoo, Do Hyun

Static information storage and retrieval

Read/write circuit

Bad bit

365 51, 365 63, 3652257, 36523003, G11C 700

Patent

active

060943823

ABSTRACT:
A row redundancy fuse box that replaces a defective row with a redundant row of an integrated circuit memory device is located between a row decoder, a row predecoder and a subarray block control circuit. By locating the row redundancy fuse box between the row decoder and the subarray block control circuit, the size of an integrated circuit memory device and the bus line loading in the device may be reduced. A row predecoder is coupled to the row redundancy fuse box and is located remote from the row decoder, the subarray block control circuit and the row redundancy fuse box. A column decoder is located adjacent the row predecoder and remote from the row decoder, the subarray block control circuit and the row redundancy fuse box. A pad layer receives and transmits external input and output signals respectively, and is located adjacent the subarray block control circuit, opposite the row redundancy fuse box. The predecoded row address bus and the row decoder overlap one another in the integrated circuit memory device. More specifically, the row decoder is preferably beneath the predecoded row address bus in the integrated circuit memory device. This can also decrease the size of the integrated circuit memory device. According to another aspect, the redundancy enable bus extends from the fuse box, up to but not beyond the predecoded row address bus.

REFERENCES:
patent: 5469388 (1995-11-01), Park
patent: 5612923 (1997-03-01), Gibson et al.
patent: 5732029 (1998-03-01), Lee et al.
patent: 5848007 (1998-12-01), Takahashi

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