Integrated circuit memory devices with high and low dopant conce

Details Integrated circuit memory devices with high and low dopant conce Integrated circuit memory devices with high and low dopant conce

1997-05-12

1999-10-19

Prenty, Mark V.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257344, 257607, H01L 2976

Patent

active

059693959

ABSTRACT:
An integrated circuit memory device includes a substrate divided into a cell array region, a core region, and a peripheral circuit region. A plurality of memory cells in the memory cell region each comprise a memory cell transistor having first spaced apart source/drain regions of the substrate with a predetermined conductivity. A sensing circuit in the core region of the substrate includes a sensing transistor having second spaced apart source/drain regions of the substrate. Each of the second source/drain regions includes high and low concentration regions of the predetermined conductivity wherein the high and low concentration regions are doped with a common dopant. A peripheral circuit in the peripheral region of the substrate includes a peripheral transistor having third spaced apart source/drain regions wherein each of the third source/drain regions has high and low concentration regions thereof. The high concentration region of the third source/drain regions has a first dopant and the low concentration region of the third source/drain region has a second dopant. Related methods are also discussed.

REFERENCES:
patent: 4878100 (1989-10-01), McDavid
patent: 5021851 (1991-06-01), Haken et al.
patent: 5324680 (1994-06-01), Lee et al.

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