Integrated circuit memory devices that map nondefective memory c

Details Integrated circuit memory devices that map nondefective memory c Integrated circuit memory devices that map nondefective memory c

1997-10-07

1998-12-08

Nelms, Davin

Static information storage and retrieval

Read/write circuit

Bad bit

36523003, 36523006, G11C 700, G11C 800

Patent

active

058480099

ABSTRACT:
Integrated circuit memory devices and operating methods map a plurality of memory cell blocks excluding defective memory cell blocks into a continuous address sequence of variable length. The memory cell blocks excluding the defective memory cell blocks, are preferably mapped to defective normal memory cell blocks, beginning at a highest memory cell block address and sequentially proceeding to lower cell block addresses, so as to generate continuous addresses for the memory cell blocks. Continuous address spaces may be provided by providing a plurality of flag blocks, a respective one of which corresponds to a respective one of the normal memory cell blocks. Each flag block contains a first indication that the corresponding normal memory cell block is nondefective, a second indication that the corresponding normal memory cell block is substituted with a redundant memory cell block, or a third indication that the corresponding normal memory cell block is substituted with another normal memory cell block. Then, upon addressing a normal memory cell block, a redundant memory cell block is substituted if the second indication is in the flag block that is associated with the selected normal memory cell block. A nondefective normal memory cell block is substituted for a selected normal cell block in response to the third indication being in the flag block that is associated with the selected normal memory cell block.

REFERENCES:
patent: 4310901 (1982-01-01), Harding et al.
patent: 4355376 (1982-10-01), Gould
patent: 5515335 (1996-05-01), Fujita et al.

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