Integrated circuit memory devices including transmission...

Details Integrated circuit memory devices including transmission... Integrated circuit memory devices including transmission...

2000-10-06

2002-05-28

Tran, M. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

C365S063000

Reexamination Certificate

active

06396756

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to integrated circuit devices, and more particularly to integrated circuit memory devices.
BACKGROUND OF THE INVENTION
Integrated circuit memory devices are widely used in consumer and commercial applications. As the integration density of integrated circuit memory devices continues to increase, it may become increasingly important to improve the layout efficiency of the integrated circuit memory device. In particular, it may be increasingly important to improve the arrangement of functional blocks, also referred to herein as parts, of the integrated circuit device, relative to one another, on an integrated circuit substrate.
FIG. 1
is a circuit diagram of an integrated circuit memory device such as a conventional Dynamic Random Access Memory (DRAM). As shown in
FIG. 1
, an input/output (I/O) selecting part
30
is positioned between a pair of first and second sense amplifying parts
10
,
20
for bit line pairs BL
1
, /BL
1
, and another input/output selecting part
30
a
is between another pair of first and second sense amplifying parts for BL
2
, /BL
2
.
A first transmission part
40
is arranged on the left side of the first sense amplifying part
10
of the bit line BL
1
, /BL
1
, BL
2
, /BL
2
to control selection of the memory cell array part
60
, and a first voltage equalizing part
50
is arranged on the left side of the first sense amplifying part
10
to control turning on/off of the first memory cell array part
60
of the bit line pairs BL
1
, /BL
1
, BL
2
, /BL
2
. Furthermore, a first memory cell array part is arranged on the left side of the first voltage equalizing part.
Likewise, a second transmission part
70
is arranged on the right side of the second sense amplifying part
20
, and a first voltage equalizing part
80
is arranged on the right side of the second transmission part
70
to control turning on/off of each pair of bit lines BL
1
, /BL
1
, BL
2
, /BL
2
. Furthermore, a second memory cell array part
90
is arranged on the right side of the second voltage equalizing part
80
.
In addition, the pairs of bit lines BL
1
, /BL
1
, BL
2
, /BL
2
are respectively extended in the horizontal directions from the first memory cell array part
60
across the first transmission part
40
to the first sense amplifying part
10
and from the first sense amplifying part
10
across the second transmission part
70
to the second memory cell array part
90
. Word lines (not shown) also vertically extend across the first and second memory cell arrays
60
,
90
. The first and second sense amplifying parts
10
,
20
amplify by detecting a difference in voltage between pairs of bit lines associated with the memory cell array parts
60
,
90
. The input/output selection part
30
selectively outputs the voltage amplified by the first and second sense amplifying parts
10
,
20
to the input/output lines IO
1
, IO
2
, /IO
1
, /IO
2
.
The operations of each of the parts that were described above are well known to those having skill in the art, and need not be described in detail herein. Moreover, it will be understood that all of the parts generally may be duplicated, in the vertical direction, for additional bit line pairs BL
3
, /BL
3
, BL
4
, /BL
4
. . . , to form an integrated circuit memory device.
In the memory cell array parts
60
,
90
, memory cells (not shown) are arranged at the crossing points of the word lines (not shown) and bit lines. The voltage equalizing parts
50
,
80
may be constructed with conventional circuits, and need not be described in detail.
In the transmission part
40
, transistors Q
4
, Q
5
are respectively connected to the bit lines BL
1
, /BL
1
, and signal PISOL is commonly transmitted to gates of the transistors Q
4
, Q
5
. Similarly, in the transmission part
70
, transistors Q
14
, Q
15
are respectively connected to the bit lines BL
1
, /BL
1
, and signal PISOR is commonly transmitted to gates of the transistors Q
14
, Q
15
.
In the sense amplifying part
10
, the drain and gate of NMOS transistor Q
6
are respectively connected to bit lines BL
1
, /BL
1
, and the drain and gate of NMOS transistor Q
7
are respectively connected to bit lines BL
1
, /BL
1
. The sources S of the transistors Q
6
, Q
7
are connected together. Likewise, in the sense amplifying part
20
, the drain and gate of PMOS transistor Q
16
are respectively connected to bit lines BL
1
, /BL
1
, and the drain and gate of PMOS transistor Q
17
are respectively connected to bit lines BL
1
, /BL
1
. The sources S of the transistors Q
16
, Q
17
are connected together. A predetermined power supply voltage Vss is supplied to the sources S of the transistors Q
6
, Q
7
during the operations of the sense amplifying part
10
, while another power supply voltage Vcc is supplied to the sources S of the transistors Q
16
, Q
17
during the operations of the sense amplifying part
20
.
In the input/output selection part
30
, the drain D and source S of transistor Q
8
are respectively connected to a bit line BL
1
and an input/output line IO
1
, while the drain D and source S of transistor Q
9
are respectively connected to bit line /BL
1
and input/output line /IO
1
.
Similarly, in the input/output selection part
30
a
, the drain D and source S of transistor Q
18
are respectively connected to a bit line BL
2
and an input/output line IO
2
, while the drain D and source S of transistor Q
19
are respectively connected to a bit line /BL
2
and an input/output line /IO
2
. Signal IOG is commonly supplied to the gates of transistors Q
8
, Q
9
, Q
18
, Q
19
.
The layout view of the circuit thus constructed is shown in FIG.
2
. As shown in
FIG. 2
, only the arrangement of the aforementioned parts relevant to the pairs of bit lines BL
1
, /BL
1
, BL
2
, /BL
2
is described. It will be understood that parts relevant to all other pairs of bit lines BL
3
, /BL
3
, BL
4
, /BL
4
. . . also may be arranged identical to those of the pairs of bit lines BL
1
, /BL
1
, BL
2
, /BL
2
. The detailed layout of the memory cell array parts
60
,
90
also are not shown.
In
FIG. 2
, the regions filled with dots indicate an N+ active region
100
for NMOS transistors Q
6
, Q
7
of a sense amplifying part
10
, N+ active regions
311
,
312
for NMOS transistors Q
8
, Q
9
of an input/output selection part
30
, N+ active regions
311
,
312
for NMOS transistors Q
18
, Q
19
of an input/output selection part
30
a
, N+ active regions
400
,
700
for NMOS transistors Q
4
, Q
5
, Q
14
, Q
15
of the transmission parts
40
,
70
, and N+ active regions
500
,
800
for NMOS transistors Q
1
, Q
2
, Q
3
, Q
11
, Q
12
, Q
13
of voltage equalizing parts
50
,
80
.
The P+ active region
200
for PMOS transistors Q
16
, Q
17
of the sense amplifying part
20
and the P+ active regions
110
,
210
for supplying substrate voltage V
BB
are designated by regions filled with triangular points.
The signal lines
510
,
810
,
410
,
710
and gates
120
,
130
,
220
,
230
,
320
,
330
to respectively transmit signals PEQL, PEQR, PISOL, PISOR may comprise polysilicon layers and designated by regions filled with slanted lines. The pairs of bit lines BL
1
, /BL
1
, BL
2
, /BL
2
also may comprise polysilicon layers, being indicated by dotted lines. The input/output lines IO
1
, IO
2
, /IO
1
, /IO
2
may be formed in metal layers, being designated by a solid line. The power lines
140
,
240
of the sense amplifying parts
10
,
20
may be formed in metal layers, being designated by a solid line.
The N+ and P+ active regions
100
,
200
are positioned at both left and right sides of N+ active regions
311
,
312
for transistors Q
8
, Q
9
, Q
18
, Q
19
of an input/output selection part
30
. A P+ active region
200
is arranged in N well
201
. The P+ active region
110
is vertically extended and arranged at the left side of the N+ active region
100
. The P+ active region
210
is also vertically extended and arranged at the right side of the N well
201
. The N+ active r

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