Integrated circuit memory devices including memory cells on...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S316000, C257SE29129, C257SE29300, C257SE21179, C438S257000

Reexamination Certificate

active

07834391

ABSTRACT:
Coupling among adjacent rows of memory cells on an integrated circuit substrate may reduced by forming the adjacent rows of memory cells on adjacent semiconductor pedestals that extend different distances away from the integrated circuit substrate. NAND flash memory devices that include different pedestal heights and fabrication methods for integrated circuit memory devices are also disclosed.

REFERENCES:
patent: 5610419 (1997-03-01), Tanaka
patent: 5635748 (1997-06-01), Nishizaka
patent: 5693552 (1997-12-01), Hsu
patent: 5949700 (1999-09-01), Furukawa et al.
patent: 6713811 (2004-03-01), Hsieh
patent: 7122425 (2006-10-01), Chance et al.
patent: 2006/0228880 (2006-10-01), McDaniel et al.
patent: 2007/0278625 (2007-12-01), Masuoka et al.
patent: 2009/0039418 (2009-02-01), Min et al.
Search Report under Section 17, GB Application No. GB0812997.5, Oct. 26, 2008.

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