Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-03-27
2001-11-13
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S300000, C257S306000
Reexamination Certificate
active
06316803
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device manufacturing method, and more particularly, to a method for manufacturing a semiconductor memory device having a contact.
2. Description of the Related Art
In general, as the dynamic random access memory (DRAM) becomes more highly integrated, the size of a cell gradually decreases, thereby decreasing the process margin in manufacturing a semiconductor device. Thus, precision in the alignment in forming a contact in the cell becomes more important.
In a DRAM, a contact in a cell array portion, particularly, a contact for connecting a storage electrode of a capacitor to a semiconductor substrate is usually formed between a bit line and a gate electrode line. Thus, securing an alignment margin to form a contact in such condition directly affects the performance of the device.
Also, a semiconductor memory device of 64M DRAM or more adopts a capacitor on bit-line (COB) structure, which results in an increase of a step difference between a cell array region and a peripheral circuit region. Accordingly, it is very difficult to secure an appropriate focus margin and form a fine pattern.
SUMMARY OF THE INVENTION
To solve the above problems, it is an object of the present invention to provide a method for manufacturing a semiconductor device having a self-aligning contact, by which a large enough alignment margin can be secured.
It is another object of the present invention to provide a semiconductor memory device manufacturing method capable of reducing the step difference between a cell array region and a peripheral region.
Accordingly, to achieve the above objects, there is provided a method for manufacturing a semiconductor device comprising the steps of forming gate electrodes on a semiconductor substrate, the gate electrodes being covered with a nitride spacer. Then, a thermal oxide layer is formed on the exposed surface of the semiconductor substrate between the gate electrodes, and an etch stop layer is then formed on the entire surface of the resultant structure having the thermal oxide layer to an appropriate thickness such that the space between the gate electrodes is not buried. Then, a first interlayer dielectric (ILD) film covering the space is formed between the gate electrodes and the top of the gate electrodes, and the first ILD film is then patterned to form a landing pad hole which exposes the spacer and the etch stop layer. Then, the etch stop layer and the thermal oxide layer are removed to expose the surface of the semiconductor substrate, and then the landing pad hole is filled with a conductive material to form a contact plug, resulting in landing pads.
Preferably, to form the landing pad hole, a first conductive layer is formed on the entire surface of the resultant structure having the landing pad hole, and the first conductive layer is etched until the surface of the first ILD film is exposed, to form the contact plug in the landing pad hole. Here, the first conductive layer is preferably formed by a chemical mechanical polishing (CMP) method or by etching back the first conductive layer.
Preferably, after forming the landing pads, the method for manufacturing the semiconductor device further comprises the steps of forming a second ILD film on the resultant structure having the landing pads. Then, the second ILD film is patterned to form a bit line contact hole which exposes the surface of a part of the landing pads, and a bit line contact plug is then formed in the bit line contact hole. Then, a bit line which is connected to the bit line contact plug is formed on the resultant structure having the bit line contact plug.
Also, preferably, after the step of forming the bit line, the manufacturing method further comprises the steps of forming a third ILD film on the resultant structure having the bit line. Then, the third ILD film is patterned to form a storage electrode contact hole which exposes the surface of the other part of the landing pads, and a storage electrode is then formed, which is connected to the semiconductor substrate via the storage electrode contact hole and the other part of the landing pads. Then, a dielectric film is formed on the storage electrode, and then an upper electrode is formed on the dielectric layer to complete a capacitor.
According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor memory device comprising the steps of forming a gate electrode on a semiconductor substrate having a cell array region and a peripheral circuit region, the gate electrode being covered with a spacer. Then, a planarized first interlayer dielectric (ILD) film is formed on the semiconductor substrate having the gate electrode, and a second ILD film is then formed on the first ILD film. Then, a remaining preventing layer is formed on the second ILD film, and the remaining preventing layer, the second ILD film and the first ILD film are patterned in sequence to form a landing pad hole which simultaneously exposes an active region of the semiconductor substrate, and a part of the spacer in the cell array region. Then, a contact plug is formed in the landing pad hole, resulting in landing pads.
According to still another aspect of the present invention, there is provided a method for manufacturing a semiconductor device comprising the steps of forming gate electrodes on a semiconductor substrate, the gate electrodes being covered with a nitride spacer. Then, a thermal oxide layer is formed on the surface of the semiconductor substrate which is exposed between the gate electrodes. Then, an etch stop layer is formed on the entire surface of the resultant structure having the thermal oxide layer to an appropriate thickness such that the space between the gate electrodes is not buried. Then, a first oxide layer is formed in the space between the gate electrodes, and then a second oxide layer is formed on the first oxide layer. Then, a polysilicon layer is formed on the second oxide layer, and the polysilicon layer, the second oxide layer, the first oxide layer, the etch stop layer and the thermal oxide layer are partially etched in sequence, to form a landing pad hole which simultaneously exposes the surface of the semiconductor substrate and a part of the spacer. Then, a landing pad is formed in the landing pad hole.
In the method for manufacturing a semiconductor device according to the present invention, a sufficient alignment margin can be secured in the formation of a landing pad without damaging the semiconductor substrate, and the step difference in the semiconductor substrate can be minimized.
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Ban Hyo-dong
Choe Hyun-cheol
Choi Chang-Sik
Hu Shouxiang
Myers Bigel & Sibley & Sajovec
Samsung Electronics Co,. Ltd.
Thomas Tom
LandOfFree
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