Integrated circuit memory devices having reduced write cycle tim

Details Integrated circuit memory devices having reduced write cycle tim Integrated circuit memory devices having reduced write cycle tim

1996-09-06

1998-08-18

Nguyen, Tan T.

Static information storage and retrieval

Read/write circuit

Differential sensing

36523006, 36518901, G11C 800

Patent

active

057966680

ABSTRACT:
An integrated circuit memory device includes a plurality of memory cells arranged in an array of rows and columns, a plurality of word lines wherein each of the word lines is associated with a predetermined row of the memory cells, and a plurality of common lines wherein each of the column lines is associated with a predetermined column of the memory cells. Each of a plurality of sense amplifiers is associated with a respective column line and each of the sense amplifiers detects a voltage difference between a pair of bit lines for the respective column and amplifies the voltage difference. A row decoder selects one of the word lines in response to a row address input during a write operation. An input/output driver receives data input during the write operation, and each of a plurality of input/output gates is connected between the input/output driver and a respective one of the column lines. A column decoder activates one of the input/output gates before the sense amplifier senses and amplifies the voltage difference. Related methods are also disclosed.

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