Static information storage and retrieval – Systems using particular element – Capacitors
Reexamination Certificate
1999-12-08
2001-01-23
Fears, Terrell W. (Department: 2824)
Static information storage and retrieval
Systems using particular element
Capacitors
C365S189090, C365S206000
Reexamination Certificate
active
06178109
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATION
This application claims the benefit of Korean Patent Application No. 98-53936, filed Dec. 9, 1998, the disclosure of which is hereby incorporated herein by reference.
FIELD OF THE INVENTION
The present invention relates generally to the field of integrated circuit memory devices, and, more particularly, to noise suppression in high-speed integrated circuit memory devices, such as a Rambus dynamic random access memory (RDRAM) device.
BACKGROUND OF THE INVENTION
Improvements in both speed and functionality of central processing units (CPUs) have generally resulted in accompanying improvements in memory devices to support the operation of these improved CPUs. One example of a memory device that has been designed to provide higher data processing speeds than conventional dynamic random access memories (DRAMs) is the Rambus DRAM (RDRAM). The Rambus DRAM typically includes a plurality of input receivers for converting the voltage level of an external data signal to a level suitable for circuitry internal to the Rambus DRAM. Each of the plurality of input receivers typically includes a differential amplifier for comparing the voltage level of the input data signal with a reference voltage. The differential amplifier generally includes a first NMOS transistor, which is gated by the input data signal, and a second NMOS transistor, which is gated by the reference voltage. When the input receivers operate simultaneously, an overlap capacitance may develop between the gate and the drain of the second NMOS transistor. As the overlap capacitance increases, the reference voltage may fluctuate to levels at which the plurality of input receivers may malfunction.
The fluctuation in the reference voltage may be characterized as noise impressed upon the reference voltage. In general, the noise level increases with distance from the source of the reference voltage. Thus, those input receivers positioned more distant from the location at which the reference voltage is applied may experience greater noise levels. An increase in the noise level may cause the input characteristics to differ between the various input receivers. Accordingly, different input receivers may yield different outputs for the same input data signal because of differences in the reference voltage level applied to the different input receivers caused by the noise.
In addition, the data set-up and hold times may also differ among the various input receivers. The input receivers typically operate in synchronization with a clock signal. The set-up time denotes the amount of time for which data must be input to an input receiver before the clock signal is transitioned while the hold time denotes the amount of time for which data must be continuously held after the clock signal is transitioned. Unfortunately, the input receivers may experience increasing margin loss in set-up time and hold time as their distance increases from the location at which the reference voltage is applied, which may cause the Rambus DRAM to malfunction.
Consequently, there exists a need for integrated circuit memory devices having improved immunity from reference voltage signal noise.
SUMMARY OF THE INVENTION
Certain objects, advantages, and features of the invention may be set forth in the description that follows and may become apparent to those skilled in the art upon examination of the following or may be learned with the practice of the invention.
These and other objects, advantages, and features of the present invention may be provided by integrated circuit memory devices that include an input receiver having a reference voltage input terminal. A conductor electrically couples the reference voltage input terminal to a reference voltage, and a capacitor is connected between the conductor and a first ground voltage. Preferably, the location of the connection between the capacitor and the conductor is selected in accordance with the electrical characteristics of the input receivers. The capacitor may serve as a filter to suppress fluctuations in a reference voltage applied to the reference voltage input terminals, which may cause the input receivers to malfunction.
In accordance with another aspect of the present invention, the integrated circuit memory devices may include a plurality of input receivers with each input receiver having a reference voltage input terminal that is coupled to the reference voltage by the conductor.
In accordance with another aspect of the present invention, a plurality of capacitors may be used to suppress the fluctuations in the reference voltage by connecting a capacitor between each of the plurality of reference voltage input terminals and the first ground voltage.
In accordance with yet another aspect of the present invention, the integrated circuit memory devices include a delay locked loop circuit that is responsive to a first clock signal and generates a second clock signal having a predetermined duty cycle. The input receivers are connected to a second ground voltage and are responsive to the second clock signal.
In accordance with still another aspect of the present invention, the second ground voltage has a magnitude that exhibits greater variability than a magnitude of the first ground voltage.
In accordance with still another aspect of the present invention, an input receiver preferably comprises a level shifter, which is responsive to an input data signal and the reference voltage, and a static cell that generates an output data signal at a logic level opposite that of the input data signal. An amplifier and a capacitance fixing circuit are preferably used to couple the level shifter to the static cell. The level shifter may be implemented as a differential comparator circuit.
In accordance with yet another aspect of the present invention, the capacitors connected between the conductor and the first ground voltage are metal oxide semiconductor (MOS) capacitors and the integrated circuit memory devices are Rambus dynamic random access memory (RDRAM) devices.
The present invention, therefore, may be used to suppress fluctuations or noise in a reference voltage applied to the reference voltage input terminals of the input receivers. The fluctuations or noise in the reference voltage may cause the input characteristics and/or the set-up and hold times of the input receivers to vary with respect to one another. Advantageously, a reduction in fluctuations or noise in the reference voltage may result in more consistent input characteristics among the input receivers and more consistency in the set-up and hold times.
REFERENCES:
patent: 4025907 (1977-05-01), Karp
patent: 4831591 (1989-05-01), Imazeki
Song Ho-sung
Yoo Jei-Hwan
Fears Terrell W.
Myers Bigel & Sibley & Sajovec
Samsung Electronics Co,. Ltd.
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