Integrated circuit memory devices having multiple data rate mode

Details Integrated circuit memory devices having multiple data rate mode Integrated circuit memory devices having multiple data rate mode

1998-12-30

2000-07-25

Mai, Son

Static information storage and retrieval

Read/write circuit

Simultaneous operations

36518902, 365238, 3652385, 365233, G11C 700

Patent

active

060943750

ABSTRACT:
Integrated circuit memory devices which are operable in both single and dual data rate modes (depending on the value of a mode select signal), include first and second memory cell arrays and first and second global input/output signal lines (GIOF, GIOS) electrically coupled to the first and second memory cell arrays, respectively. Decoder and data transmission circuits are provided and these circuits are responsive to the mode select signal and column address signals. These circuits enable operation in both single and dual data rate modes and perform the functions of simultaneously transferring read data on the first and second global input/output lines to first and second data lines, respectively, during a first read time interval when a first column address signal is in a first logic state and simultaneously transferring read data on said first and second global input/output lines to the second and first data lines, respectively, during a second read time interval when the first column address signal is in a second logic state opposite the first logic state.

REFERENCES:
patent: 5513327 (1996-04-01), Farmwald et al.
patent: 5680365 (1997-10-01), Blankenship
patent: 5726950 (1998-03-01), Okamoto
patent: 5973989 (1999-10-01), Pawlowski
patent: 5991232 (1999-11-01), Matsumura et al.
Search Report, GB 9808824.8, Jul. 15, 1998.

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