Static information storage and retrieval – Read/write circuit – Simultaneous operations
Reexamination Certificate
2000-05-23
2001-08-28
Mai, Son (Department: 2818)
Static information storage and retrieval
Read/write circuit
Simultaneous operations
C365S189020, C365S233100
Reexamination Certificate
active
06282128
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuit devices and methods of operating integrated circuit devices, and more particularly to integrated circuit memory devices and methods of operating integrated circuit memory devices.
BACKGROUND OF THE INVENTION
Computer systems typically include a central processing unit (CPU) for performing commands and a main memory for storing data and programs required by the CPU. Thus, increasing the operational speed of the CPU and reducing the access time of the main memory can enhance the performance of the computer system. As will be understood by those skilled in the art, a synchronous DRAM (SDRAM) operates according to control of a system clock and typically provides a short access time when uses as a main memory.
In particular, the operation of the SDRAM is controlled in response to pulse signals generated by transitions of a system clock. Here, the pulse signals are generated during a single data rate SDR mode or a dual data rate DDR mode. The SDR mode generates pulse signals with respect to transitions in one direction (e.g., pulse signals of ‘high’ to ‘low’ or vice versa) to operate a DRAM device. However, the DDR mode generates pulse signals with respect to transitions in both directions (e.g., pulse signals of ‘high’ to ‘low’ and vice versa) to operate the DRAM device.
The DDR mode enables a memory device to have wide bandwidth operation. Thus, the DDR mode is very helpful when making an ultra-high speed SDRAM. However, to implement the DDR mode, the layout area of the memory device typically must be increased because twice as many data lines may need to be provided. Also, in the DDR mode compared with the SDR mode, set-up time and data hold time between data and the clock during reading and writing are reduced, so that auxiliary circuits for delaying an external clock are often necessary. This requirement may lead to further increase in the size of the memory chip. Therefore, only memory devices for ultra-high speed systems typically utilize the DDR mode, whereas other memory devices typically utilize the SDR mode.
Notwithstanding these known aspects of conventional memory devices, there continues to exist a need for improved memory devices and methods of operating same.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide improved integrated circuit memory devices and methods of operating same.
It is another object of the present invention to provide integrated circuit memory devices which have the capability of reading and writing data in both single and dual data rate modes and methods of operating same.
These and other objects, features and advantages of the present invention are provided by integrated circuit memory devices which are operable in both single and dual data rate modes depending on the value of a mode select signal (PSDR). According to a preferred embodiment of the present invention, an integrated circuit memory device includes first and second memory cell arrays and first and second global input/output signal lines (GIOF, GIOS) electrically coupled to the first and second memory cell arrays, respectively. In addition, decoder and data transmission circuits are provided and these circuits are responsive to the mode select signal and column address signals. These circuits also enable operation in both single and dual data rate modes. In particular, during a dual data rate mode, these circuits perform the functions of simultaneously transferring read data on the first and second global input/output lines to first and second data lines, respectively, during a first read time interval when a first column address signal is in a first logic state (e.g., logic 0) and for simultaneously transferring read data on said first and second global input/output lines to the second and first data lines, respectively, during a second read time interval when the first column address signal is in a second logic state (e.g. logic 1). These circuits preferably include a first output transfer circuit having an input electrically coupled to the first global input/output signal line and first and second outputs electrically coupled to the first and second data lines, respectively, and a second output transfer circuit having an input electrically coupled to the second global input/output signal line and first and second outputs electrically coupled to the first and second data lines, respectively. First and second input drivers are also provided. The first input driver has an input electrically coupled to the first data line (but not the second data line) and first and second outputs electrically coupled to the first and second global input/output lines, respectively. The second input driver has an input electrically coupled to the second data line (but not the first data line) and first and second outputs electrically coupled to the first and second global input/output lines, respectively.
According to another embodiment of the present invention, a preferred method of operating an integrated circuit memory device having first and second memory arrays therein includes the steps of simultaneously transferring read data from the first and second memory arrays to the first and second data lines, respectively, during a first read time interval, in response to a first address signal in a first logic state, and simultaneously transferring read data from the first and second memory arrays to the second and first data lines, respectively, during a second read time interval, in response to the first address signal in a second logic state opposite the first logic state. These steps are performed during a dual data rate mode. In addition, during a single data rate mode, steps are performed to transfer read data from the first memory array to the first data line, in response to the first address signal in the first logic state and transfer read data from the second memory array to the first data line, in response to the first address signal in the second logic state.
REFERENCES:
patent: 5818785 (1998-10-01), Ohshima
patent: 6094375 (2000-07-01), Lee
patent: 6097640 (2000-08-01), Fei et al.
patent: 6151271 (2000-11-01), Lee
Mai Son
Myers Bigel & Sibley & Sajovec
Samsung Electronics Co,. Ltd.
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