Integrated circuit memory devices having improved refresh mode a

Details Integrated circuit memory devices having improved refresh mode a Integrated circuit memory devices having improved refresh mode a

1998-12-07

1999-12-14

Nelms, David

Static information storage and retrieval

Read/write circuit

Data refresh

365239, G11C 700

Patent

active

060026294

ABSTRACT:
Integrated circuit memory devices include an array of memory cells and a row address generator circuit which generates first and second different sequences of addresses during first and second refresh modes, respectively, and also repeats at least one of the addresses in the first sequence as an address in the second sequence when transitioning from the first refresh mode to the second refresh mode. The generator circuit may also perform the function of generating row addresses during the first and second refresh modes with the most significant bit of a row address being toggled with each consecutive row address during the first refresh mode. The first refresh mode may be a CAS-before-RAS refresh mode, the second refresh mode may be a self-refresh mode and the address in at least one of the first and second periods of the self-refresh mode may be equivalent to an address in the last period of a preceding CAS-before-RAS refresh mode when transitioning from the first refresh mode to the second refresh mode. This repetition in addressing prevents one or more row of memory cells from being skipped when transitioning from one refresh mode to another refresh mode.

REFERENCES:
patent: 4809233 (1989-02-01), Takemae
patent: 4939695 (1990-07-01), Isobe et al.
patent: 4943960 (1990-07-01), Komatsu et al.
patent: 5315557 (1994-05-01), Kim et al.
patent: 5629898 (1997-05-01), Idei et al.
patent: 5822264 (1998-10-01), Tomishima et al.

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