Static information storage and retrieval – Read/write circuit – Testing
Patent
1998-07-28
2000-04-18
Nelms, David
Static information storage and retrieval
Read/write circuit
Testing
36523006, G11C 800
Patent
active
060523204
ABSTRACT:
Integrated circuit memory devices having merged data test capability include first and second memory cell arrays in first and second blocks of memory, respectively, a first global input/output line and switches for enabling transfer of data from the first memory cell array to the first global input/output line in response to a first merged data test control signal P1 and enabling transfer of data from the second memory cell array to the first global input/output line in response to a second merged data test control signal P2. A highly integrated merged data test circuit is also provided with test cells therein and each test cell is capable of testing multiple memory cell arrays in at least two blocks of memory. A first merged data test circuit is provided which has a first input electrically coupled to the first global input/output line and a first output which generates first and second error signals upon detection of a failure in the first and second memory cell arrays, respectively.
REFERENCES:
patent: 5561636 (1996-10-01), Kirihata et al.
patent: 5606528 (1997-02-01), Ikeda
patent: 5912899 (1999-06-01), Kim et al.
Nelms David
Samsung Electronics Co,. Ltd.
Tran M.
LandOfFree
Integrated circuit memory devices having highly integrated merge does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated circuit memory devices having highly integrated merge, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit memory devices having highly integrated merge will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2341679