Integrated circuit memory devices having cross-coupled isolation

Details Integrated circuit memory devices having cross-coupled isolation Integrated circuit memory devices having cross-coupled isolation

1998-06-24

1999-09-14

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Simultaneous operations

365205, 365220, G11C 1604

Patent

active

059532599

ABSTRACT:
Preferred integrated circuit memory devices have the capability of connecting a sense amplifier to multiple arrays of memory one-at-a-time or simultaneously, in response to first and second control signals, respectively. These memory devices include first and second memory arrays which have first and second pairs of differential input/output lines electrically coupled thereto, respectively. A sense amplifier is also provided having first and second pairs of differential input/output lines. To provide independent or simultaneous access to the first and second memory arrays by the sense amplifier, preferred isolation and equalization circuits are provided. With these circuits, a first electrical connection can be formed between the first pairs of differential input/output lines of the first memory array and the sense amplifier and a second electrical connection can be simultaneously formed between the second pairs of differential input/outlput lines of the second memory array and the sense amplifier, when a control signal line is in a first logic state (e.g., logic 0). These preferred isolation and equalization circuits also preclude simultaneous formation of the first and second electrical connections when the control signal line is in a second logic state (e.g., logic 1).

REFERENCES:
patent: 4736343 (1988-04-01), Hidaka et al.
patent: 5274585 (1993-12-01), Suyama et al.
patent: 5701268 (1997-12-01), Lee et al.
patent: 5726939 (1998-03-01), Cho et al.

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