Integrated circuit memory devices having built-in self test base

Details Integrated circuit memory devices having built-in self test base Integrated circuit memory devices having built-in self test base

1998-10-14

2000-07-18

Nelms, David

Static information storage and retrieval

Read/write circuit

Bad bit

365201, G11C 700

Patent

active

060916494

ABSTRACT:
An integrated circuit memory device includes a memory access circuit operative to generate an address. A redundant memory is responsive to the memory access circuit and has a plurality of memory locations, the redundant memory providing access to one of a first memory location and a second memory location responsive to an address generated by the memory access circuit and to a redundancy control signal. A self-testing redundancy control circuit is responsive to the memory access circuit and to the redundant memory and operative to apply a redundancy control signal to the redundant memory in response to a comparison of test data stored in a target memory location of the redundant memory with data retrieved from the target memory location. Related operating methods are also discussed.

REFERENCES:
patent: 5659551 (1997-08-01), Huott et al.
patent: 5825783 (1998-10-01), Momohara
patent: 5841711 (1998-11-01), Watanabe
patent: 5859804 (1999-01-01), Hedberg et al.
patent: 5864577 (1998-06-01), Johnston et al.

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