Integrated circuit memory devices and operating methods that...

Details Integrated circuit memory devices and operating methods that... Integrated circuit memory devices and operating methods that...

2005-05-24

2005-05-24

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Read/write circuit

Serial read/write

C365S219000, C365S201000, C365S233100

Reexamination Certificate

active

06898139

ABSTRACT:
Integrated circuit memory devices include a memory cell array that is configured to output data bits in parallel at a first data rate. An output circuit is configured to serially output the data bits to an external terminal at the first data rate in a normal mode of operation, and to serially output the data bits to the external terminal at a second data rate that is lower than the first data rate in a test mode of operation. Accordingly, the memory cell array can operate at a first data rate while allowing the output circuit to output data to an external terminal at a second data rate that is lower than the first data rate, in a test mode of operation.

REFERENCES:
patent: 5933379 (1999-08-01), Park et al.
patent: 6163491 (2000-12-01), Iwamoto et al.
patent: 6212113 (2001-04-01), Maeda
patent: 6301182 (2001-10-01), Tanaka

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