Integrated circuit memory devices and controlling methods that s

Details Integrated circuit memory devices and controlling methods that s Integrated circuit memory devices and controlling methods that s

1998-06-25

2000-05-16

Nelms, David

Static information storage and retrieval

Read/write circuit

Simultaneous operations

36518905, 365201, G11C 1604

Patent

active

060646012

ABSTRACT:
Integrated circuit memory devices can reduce write time during a write cycle of a parallel bit test mode. The memory devices include a simultaneous column select line activation circuit that simultaneously activates at least two of the plurality of column select lines during a write cycle of a parallel bit test mode. Therefore, during the write cycle, at least two bit lines are simultaneously connected to one input and output line since at least two column select lines are simultaneously activated by the simultaneous column select line activation circuit. Accordingly, data is simultaneously written to the memory cells connected to at least two bit lines through the input and output line.

REFERENCES:
patent: 5202853 (1993-04-01), Choi
patent: 5301142 (1994-04-01), Suzuki et al.
patent: 5416741 (1995-05-01), Ohsawa
patent: 5568434 (1996-10-01), Jeon
patent: 5748641 (1998-05-01), Ohsawa
patent: 5809225 (1998-09-01), Ohsawa et al.

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