Static information storage and retrieval – Read/write circuit – Having fuse element
Reexamination Certificate
1999-07-01
2001-04-10
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Having fuse element
C365S200000
Reexamination Certificate
active
06215715
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of integrated circuit memories, and, more particularly, to the use of fuses in an integrated circuit memory to disable defective memory storage cells.
BACKGROUND OF THE INVENTION
To improve the yield of an integrated circuit memory, it is common practice to include redundancy circuits in the device that can be used to repair defective memory storage cells that are unusable as a result of damage incurred during the fabrication process. The redundancy circuits comprise a spare memory decoder and a spare memory array that can replace unusable storage cells from the main memory array.
A high-level block diagram of a conventional integrated circuit memory
8
that includes redundancy circuits is shown in FIG.
1
. The integrated circuit memory
8
includes a main memory decoder
10
that is comprised of a plurality of normal decoder components
11
-
14
and a driving decoder
15
. Each normal decoder component
11
-
14
is coupled to a word line driver
16
-
19
. The word line drivers are coupled to a multi-dimensional, main memory array
20
of storage cells and are used to select a particular word in the main memory array
20
. In addition to the main memory decoder
10
, a spare memory decoder
21
is wired in parallel to the normal decoder components
11
-
14
and a spare word line driver
23
is wired in parallel to the word line drivers
16
-
19
to provide redundancy through a spare memory array
24
.
For purposes of illustration, the main memory array
20
is assumed to be a two-dimensional array of rows and columns with the main memory decoder
10
being a row decoder for selecting a row of storage cells from array
20
. The main memory array
20
includes 2
n+1
rows of storage cells that are selected by word lines WL
0
-WL
2
n+1
−1. Accordingly, N+1 address bits, identified as RA
0
-RAN, are used to access the rows in the main memory array
20
.
The integrated circuit memory
8
of
FIG. 1
operates as follows. When the row address strobe (RAS) line is driven into an active mode, the main memory decoder
10
will receive a row address after some initial predecoding. The normal decoder components
11
-
14
are used to decode all but the two lowest order bits. The two lowest order bits are decoded by the driving decoder
15
. It therefore follows that the normal decoder components
11
-
14
decode 2
n−1
word lines while the driving decoder
15
decodes four word lines, which results in a total of 2
n−1
*2
2
=2
n−1
word lines being decoded overall.
In addition to providing the row address to the main memory decoder
10
, the row address is also provided to the spare memory decoder
21
. The spare memory decoder
21
decodes the same bits, RA
2
-RAN as the normal decoder components
11
-
14
and selects the appropriate spare word line from the spare memory array
24
through the spare word line driver
23
and the driving decoder
15
. Specifically, when defects are encountered in a word selected from the main memory array
20
, an output signal XRED is enabled to deactivate the normal decoder component
11
-
14
that decoded the row corresponding to the defective word. In addition to deactivating the appropriate normal decoder component
11
-
14
, the output signal XRED also activates the spare word line driver
23
to allow access to the spare memory array
24
, which serves as a replacement for the defective row in the main memory array
20
.
While the aforementioned approach can be effective in providing the necessary redundancy to maintain the yield of the integrated memory circuit
8
, it nevertheless can suffer from a significant drawback. The XRED signal that controls access to the redundancy path generally must be enabled before the address is decoded by the main memory decoder
10
. Otherwise, a race condition can ensue in which the word lines to both the main memory array
20
and the spare memory array
24
corresponding to the row address will be selected. To avoid this condition, the main memory decoder
10
decodes the address after a defined delay to allow the XRED signal to propagate and disable the correct normal decoder component
11
-
14
and activate the spare word line driver
23
, if necessary. Unfortunately, this delay can lower the operating speed of the integrated circuit memory.
SUMMARY OF THE INVENTION
Certain advantages of the invention will be set forth in the description that follows and will become apparent to those skilled in the art upon examination of the following or may be learned with the practice of the invention.
To achieve the advantages, the present invention is generally directed to integrated circuit memory devices that include a two-dimensional memory array in which the first and second dimensions extend in first and second directions respectively. The memory devices further include a decoder for the first dimension and a plurality of fuses between the decoder and the memory array.
In accordance with one aspect of the invention, the fuses are arranged such that the relative spacing between the fuses proceeds substantially along the second direction.
In accordance with another aspect of the invention, the fuses are oriented lengthwise in the first direction.
By arranging the plurality of fuses between the decoder and the memory array, when a defective storage cell is encountered, the appropriate fuse can be cut to physically segregate the decoder from the defective cell. This can allow the memory to operate without requiring delay to be added for switching to a spare or redundant memory array of storage cells. Memory speed can therefore be increased.
Moreover, by arranging the fuses such that the relative spacing between the fuses proceeds substantially along the direction not corresponding to the dimension being decoded and orienting the fuses lengthwise in the direction corresponding to the dimension being decoded, the layout area for the memory device can be reduced and preferably minimized.
REFERENCES:
patent: 5323348 (1994-06-01), Mori et al.
patent: 5532966 (1996-07-01), Poteet et al
patent: 0 213 044 (1987-03-01), None
patent: 0 464 577 A2 (1992-01-01), None
EPO Search Report, 99305059.0, Mar. 30, 2000.
Lee Kyu-Chan
Yi Chul-woo
Myers Bigel & Sibley & Sajovec
Nelms David
Samsung Electronics Co,. Ltd.
Tran M.
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