Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-09-20
2002-08-06
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S231000, C438S232000, C438S301000, C438S305000, C438S306000
Reexamination Certificate
active
06429062
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to integrated-circuit manufacturing and, more particularly, to a method for forming MOS transistors. A major objective is to provide shallower PMOS source/drain extension regions.
Much of modern progress is associated with the increasing prevalence of computers, which, in turn, has been made possible by advances in integrated-circuit manufacturing technology. These advances have allowed ever-smaller circuit elements to be fabricated, providing for faster speeds and greater functional density. Each reduction in circuit element sizes poses a new set of challenges to be addressed.
One prevalent technology is CMOS—which stands for “complementary metal-oxide-silicon. “Complementary” refers to the usage of two opposing types of transistors—NMOS and PMOS. In either type, a gate voltage controls conduction between a source and a drain. The conduction is along a “channel” that is spaced from the gate by a silicon dioxide layer, referred to as a “gate oxide”. The sources and drains are defined by introducing an appropriate dopant into crystalline silicon regions. In the case of an NMOS transistor, the source and drain are formed using n-type dopants (which provide electrons as current carriers); in the case of a PMOS transistor, the source and the drain are formed using p-type dopants (which provide electron-holes as current carriers).
For each transistor, the channel separates the source and the drain from each other. To reduce what is known as a “hot-carrier effect”, each source and each drain can include a lightly-doped extension that separates a respective heavily doped “deep” source/drain region from the channel. The channel then separates the source extension from the drain extension (also known as a “lightly doped drain” or “LDD”).
A CMOS transistor operates by controlling the carrier population in and below the channel. In the case of an NMOS transistor, application of a positive gate voltage tends to deplete the channel of negative-charge carriers, namely, electrons, and attract to the channel positive-charge carriers, namely, electron holes. In the case of a PMOS transistor, application of a negative gate voltage tends to deplete the channel of positive-charge holes and attract negative-charge electrons.
The effect of a given voltage varies inversely with the volume of a gate region in and below the channel. The gate region corresponds to the channel region less depletion regions associated with the p
boundaries that lie between the channel region and the source and drain extensions. The deeper the source/drain extension regions and the more the source/drain extension regions extend under the gate, the lower the gate-region volume that must be controlled by the gate voltage.
A typical integrated-circuit manufacturing method is described below. A gate oxide layer is deposited on crystalline silicon and polysilicon is deposited on the gate oxide. These two layers are photolithographically patterned using a high-energy plasma etch; this defines the transistor gate. Oxide is then grown on the silicon exposed by the etch to anneal damage due to the plasma. A relatively light implant is performed to define the source and drain extensions.
After some intermediate processing steps, silicon dioxide is deposited over the integrated-circuit structure and anisotropically etched to leave sidewall spacers. Additional silicon dioxide deposited. A heavy source/drain implant is performed through the deposited silicon. The gate sidewall spacers ensure that the heavily doped deep source/drain regions do not extend as far under the gate as the lightly doped source/drain regions do. Finally, a submetal dielectric layer is added and an interconnect structure is formed to connect the transistors.
As device dimensions shrink, control over each of the process steps becomes more critical. In particular, the source/drain extension implant must be carefully controlled. If the extension implant is too deep and/or extends to far under the gate, the gate-region volume is reduced. In this case, the transistor reacts too sensitively to (e.g., noise-induced) voltage variations so that device operation is unreliable. The reduced gate threshold voltage due to reduced gate depletion regions is known as the “short-channel effect”.
NMOS transistors are afflicted by a “reverse short-channel effect”, a seemingly paradoxical increase in threshold voltage for short-channel MOS transistors. C. S. Rafferty, H. H. Vuong, S. A. Eshraghi, M. D. Giles, and M. R. Pinto, S. J. Hillenius in “Explanation of Reverse Short Channel Effect by Defect Gradients”, IEEE IEDM (International Electronics Device Meeting) 1993, p. 311-314, have shown that the reverse short-channel effect is due to a channel impurity flux to the surface due to surface recombination of interstitials under the gate. In fact, M. E. Rubin, S. Saha, J. Lutze, F. Nouri, G. Scott, and D. Pramanik, in “Interface Interstitial Recombination Rate and the Reverse Short Channel Effect” Materials Research Society Symposium Proceedings, Vol. 568, 1999, pp. 213-218, show that adding nitrogen to the gate oxide to reduce the interstitial recombination rate reduces the gate threshold voltage.
On the other hand, the (non-reverse) short-channel effect remains a concern. In principal, it can be addressed using precisely controlled shallow implants. A shallow implant can be achieved using low implant energies; precise control can be achieved removing atoms in the implant beam with energies that vary too much from the nominal implant energy. Such filtering can be achieved by magnetically bending an implant beam and physically selecting for implanting only those atoms that bend an amount corresponding to the desired implant energy.
Precise filtering is most readily achieved with high energy implants. Implant energy correlates with implant depth and with the atomic mass of the implant species.
Returning to the (non-invasive) short-channel effect, it can be addressed by using lower energy implant beams to reduce implant penetration into the silicon crystal substrate. The implants require filtering to remove unwanted energy ranges from the implant beam. This filtering can be performed by bending an implant beam and removing beam components that do not bend at an appropriate rate (because the components have particles heavier or lighter than the particles desired for the implant.)
The filtering of unwanted energy ranges is most effective for higher energy implants. The energy associated with a given implant correlates positively with the desired depth of the implant and the atomic mass of the implant species. Thus, depth control for shallow implants of light dopants is problematic, requiring more expensive and more complex equipment.
Boron, the prevalent p-type dopant, is also relatively light. Thus, control over shallow p-type implants is problematic. This makes the short-channel effect a serious concern for sub 0.2 micron PMOS transistors. While implant depth control can be enhanced.
The filtering is most selective for higher energies. At low energies it becomes more difficult to filter out unwanted energy ranges, and thus control the implant depth. For a given desired implant depth, using more complex procedures and more expensive filtering equipment, a simpler, more economical, and more reliable method of controlling spacer depth for PMOS transistors is desired.
SUMMARY OF THE INVENTION
The present invention provides for implanting through a blocking layer of material that promotes interstitial recombination at its interface with crystalline silicon better than does a conventionally grown oxide layer. For example, the blocking layer can be of carbon-bearing silicon dioxide such as that resulting from a TEOS oxide deposition. The invention applies most favorably to boron or other p-type source/drain extension implants for a PMOS transistor.
The method can begin with the formation of a gate oxide layer and then deposition of a polysilicon layer. A plasma etch can be used to pattern these layers to define gates and so that the
Gurley Lynne A.
Koninklike Philips Electronics N.V.
Niebling John F.
Zawilski Peter
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