Integrated circuit layout design

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Reexamination Certificate

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Details

C430S030000, C430S313000, C430S315000, C716S030000

Reexamination Certificate

active

07862962

ABSTRACT:
Provided is a method including layout design of an integrated circuit. A first pattern is provided. The first pattern includes an array of dummy line features and a plurality of spacer elements abutting the dummy line features. A second pattern is provided. The second pattern defines an active region of an integrated circuit device. An edge spacer element of the active region is determined. A dummy line feature of the array of dummy line features is biased (e.g., increased in width), the dummy line feature is adjacent an edge spacer element.

REFERENCES:
patent: 2008/0179705 (2008-07-01), Noelscher et al.
patent: 2010/0183958 (2010-07-01), Inaba

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