Integrated circuit interconnect lines having sidewall layers

Details Integrated circuit interconnect lines having sidewall layers Integrated circuit interconnect lines having sidewall layers

1998-07-23

2002-05-21

Loke, Steven (Department: 2811)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S652000, C438S654000, C438S687000, C438S669000, C438S671000, C438S672000, C438S674000, C438S675000, C438S696000, C438S622000, C257S751000, C257S762000

Reexamination Certificate

active

06391771

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the fabrication of semiconductor device interconnect lines having diffusion barrier sidewalls and to the fabrication of semiconductor interconnect lines having sidewalls which compensate for misalignment between a line pattern and an underlying contact.
BACKGROUND OF THE INVENTION
A semiconductor device such as an IC (integrated circuit) generally has electronic circuit elements such as transistors, diodes and resistors fabricated integrally on a single body of semiconductor material. The various circuit elements are connected through conductive connectors to form a complete circuit which can contain millions of individual circuit elements. Advances in semiconductor materials and processing techniques have resulted in reducing the overall size of the IC while increasing the number of circuit elements. Additional miniaturization is highly desirable for improved IC performance and cost reduction. Interconnects provide the electrical connections between the various electronic elements of an IC and they form the connections between these elements and the device's external contact elements, such as pins, for connecting the IC to other circuits. Typically, interconnect lines form the horizontal connections between the electronic circuit elements while conductor filled vias form the vertical connections between the electronic circuit elements, resulting in layered connections.
The materials and dimensions of the interconnect lines are important for the performance and cost of present and future highly miniaturized IC devices. Typically, low resistance metals such as Al, Al/Cu alloys (i.e. alloys predominantly containing Al) and W find widespread use as interconnect line materials. Compared with these materials, Cu and Cu alloys (i.e. alloys predominantly containing Cu) have a lower resistance and are thus more desirable materials for interconnect lines. However, Cu is known to diffuse from the line into the device, causing malfunction or failure.
Conventional fabrication techniques for Cu or Cu alloy interconnect lines are illustrated in
FIGS. 1A-1G
. As shown in
FIG. 1A
, one or more interconnects, such as lines
110
and
112
, are formed on a semiconductor substrate
114
in a gapfill insulator
115
. One or more via holes such as
120
and
122
(
FIG. 1A
) are formed in insulating layer
116
. Bottoms
124
and
126
of via holes
120
and
122
expose the top surface of interconnects
110
and
112
respectively. As shown in
FIG. 1A
, interconnects
110
and
112
are interposed between semiconductor substrate
114
and via holes
120
and
122
respectively. Alternately, via holes such as
120
and
122
can be in direct contact with a semiconductor substrate, such as a semiconductor material or other electronic elements. As shown in
FIGS. 1A-1G
, insulator
115
is deposited between interconnects
110
and
112
. Alternately, insulator
115
can also be deposited on interconnects
110
and
112
in which case the via holes need to be formed through insulator
115
in order to expose the surface of the interconnects. Also, insulators
115
and
116
may comprise the same material.
A Cu barrier layer
130
which provides a barrier to Cu diffusion is deposited on the inside surfaces of via holes
120
and
122
, and on the exposed surface of insulating layer
116
, see FIG.
1
B. Layer
130
can also function as an adhesion promoter. As shown in
FIG. 1C
, Cu or Cu alloy via plugs
132
and
134
are formed in lined via holes
120
and
122
respectively. A Cu or Cu alloy layer
136
is deposited on via plugs
132
and
134
and on layer
130
which extends on the surface of insulator layer
116
. Cu lines
138
and
140
(
FIG. 1D
) are patterned by positioning a photo mask, a hard mask
142
or a combination of a photo and a hard mask on layer
136
. This is followed by anisotropic etching of layers
136
and
130
, to completely remove any metal between Cu lines
138
and
140
. As depicted in
FIG. 1E
, mask
142
is removed and a dielectric layer
144
is deposited on lines
138
,
140
and on the exposed surface of layer
116
. Lines
138
and
140
are provided with a Cu diffusion barrier layer only at the bottom surface of each line (i.e. the surface of the line facing towards the semiconductor substrate). The top surface
145
and side surfaces
146
and
147
of lines
138
and
140
are in direct contact with dielectric layer
144
, thus allowing Cu diffusion into layer
144
and subsequently into other components of the device.
An alternate conventional process (not shown) involves Cu plug fill, followed by removal of excess Cu, such that Cu is present only in the via. This is followed by the deposition of consecutive layers of barrier material, Cu or Cu alloy and barrier layer. The layer stack is then etched to form a Cu or Cu alloy line having top and bottom barrier layers. This technique does not provide side barrier layers.
An additional alternate conventional process for fabricating Cu or Cu alloy lines is illustrated in
FIG. 1F
showing a structure similar to the structure of
FIG. 1C
but having an additional top layer
150
comprising a Cu barrier material, which is deposited on Cu or Cu alloy layer
152
. Layer
154
of the structure shown in
FIG. 1F
is a Cu barrier layer similar to barrier layer
130
of FIG.
1
C. Cu lines
156
and
158
(
FIG. 1G
) are fabricated by anisotropic etching similar to the process described in connection with
FIG. 1D
except that the structure illustrated in
FIG. 1G
requires anisotropic etching of top Cu barrier layer
150
in addition to anisotropic etching of Cu layer
152
and Cu barrier layer
154
. As shown in
FIG. 1G
, the top Cu barrier layer
150
provides a barrier against Cu diffusion through the top surface of lines
156
and
158
but this structure does not prevent Cu diffusion through the side surfaces of lines
156
and
158
.
IC fabricating techniques which involve the alignment between an interconnect line and an underlying contact, such as a via plug, are very important for IC performance. A relatively small misalignment between the line and the underlying contact can cause trench formation in the contact, resulting in reduced IC yield and reduced reliability. The commonly used Cu or Cu alloy fabrication techniques for forming lines on vias, as illustrated in
FIGS. 1A-1G
, can also be used for the creation of connector lines comprising other metals such as Al/Cu or W. These metals usually do not require a diffusion barrier layer to prevent diffusion of metal into the structure but may instead require diffusion barriers to prevent diffusion of substances, for example fluorine, from dielectric materials into Al, Al/Cu or W. Also, metals such as Al/Cu or W may require adhesion promotion layers.
In order to fabricate metal lines, it is necessary to pattern the lines by providing an etch mask on the metal layer as shown in FIG.
2
A. An IC structure such as described in connection
FIG. 1A
, is provided with an adhesion promoting or barrier layer
210
, upon which a metal layer
212
is deposited. Using methods and materials which are well known to those of ordinary skill in the art, a mask such as a photoresist or hard mask or a combination of photoresist and hard mask, is prepared on metal layer
212
in order to subtractively etch this layer such that interconnect lines are formed on via plugs
218
and
220
. Ideally, the mask should be in good alignment with the underlying via plug, as is illustrated in
FIG. 2A
wherein mask component
214
is in good alignment with via plug
218
. However, it is difficult to dependably achieve good alignment under actual manufacturing conditions and mask misalignments, such as mask component
216
(
FIG. 2A
) which is misaligned with via plug
220
, occur from time to time particularly in highly miniaturized IC devices. Anisotropic etching is used to form lines
222
and
224
as illustrated in FIG.
2
B. Insulating layer
226
is commonly used as an etch stop. As is shown in
FIG. 2B
, conventional a

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