Integrated circuit insulated electrode forming methods using...

Details Integrated circuit insulated electrode forming methods using... Integrated circuit insulated electrode forming methods using...

1998-08-14

2001-02-13

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S649000, C438S655000, C438S657000, C438S785000, C438S791000

Reexamination Certificate

active

06187676

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to integrated circuit devices and fabrication methods, and more particularly to insulated electrodes for integrated circuits and methods of forming the same.
BACKGROUND OF THE INVENTION
Insulated electrodes are widely used in integrated circuit devices. For example, integrated circuit field effect transistors generally include spaced apart source and drain regions in an integrated circuit substrate with an insulated gate electrode on the substrate therebetween.
As the integration density of integrated circuits continues to increase, linewidths are being reduced to below a quarter micron. Unfortunately, as linewidths are reduced, it can become increasingly difficult to provide low resistance insulated electrodes with low defects. In order to provide low resistance insulated electrodes, multilayer electrodes including an insulating layer, a conductive layer on the insulating layer and a metal silicide layer on the conductive layer have been provided. For example, insulated gate electrodes including an oxide layer on an integrated circuit substrate, a doped polysilicon layer on the oxide layer and a metal silicide layer such as titanium silicide on the doped polysilicon layer, have been provided. Unfortunately, it may be difficult to fabricate these insulated electrodes at submicron linewidths with low defects.
FIGS. 1 and 2
are cross-sectional views of conventional gate electrodes which illustrate the formation of undesired silicon protrusion defects in a metal silicide layer.
More specifically, referring to
FIG. 1
, a gate electrode includes a gate oxide layer
12
on an integrated circuit substrate, such as a silicon semiconductor substrate
10
. A conductive polysilicon layer
14
, a barrier metal layer
16
and a metal silicide layer
18
are formed on the gate oxide layer
12
.
The metal silicide layer
18
may be titanium silicide, which may be formed by sputtering. During formation of the titanium silicide layer, an irregular region wherein the composition ratio of titanium and silicon is not uniform, may be formed.
After formation of the titanium silicide layer
18
, an etch mask such as a layer of Low Pressure Chemical Vapor Deposited (LPCVD) silicon nitride
20
may be formed on the metal silicide layer
18
. During formation of the LPCVD silicon nitride layer
20
, the integrated circuit substrate may be exposed to a high temperature, for example about 760° C., that is higher than the phase transition temperature of the titanium silicide. Accordingly, the titanium suicide layer
18
forms a structure with the most stable composition ratio of titanium and silicon. However, surplus silicon in the titanium silicide layer
18
may form a silicon protrusion
22
which protrudes from the titanium silicide layer
18
into the silicon nitride layer
20
. The silicon protrusion
22
can cause short circuits between adjacent gate electrodes, thereby impacting the reliability and/or yield of the integrated circuit.
FIG. 2
is a cross-sectional view of another embodiment of a conventional gate electrode. As was the case in
FIG. 1
, an insulating layer such as an oxide layer
12
is formed on an integrated circuit substrate, such as a silicon semiconductor substrate
10
. A conductive layer such as a doped polysilicon layer
14
, a barrier layer
16
and a metal silicide layer
18
are formed on the oxide layer
12
. In contrast with
FIG. 1
, however, in order to reduce the growth of silicon protrusions
22
, a Plasma Enhanced Chemical Vapor Deposited (PECVD) silicon nitride layer
24
is used as an etch mask, rather than an LPCVD silicon nitride layer. The PECVD silicon nitride
24
layer may be formed on the titanium silicide layer
18
at low temperatures, such as about 400° C.
A sidewall spacer
26
is also generally formed as part of a conventional self-aligned contact process. The sidewall spacer
26
may need to have the same etching selectivity as an interlayer insulating layer that is used for metal wiring, so that LPCVD silicon nitride is generally used for the sidewall spacer
26
. Unfortunately, during the formation of the LPCVD silicon nitride sidewall spacer
26
, a silicon protrusion
28
may be produced from the sidewall of the metal silicide layer
18
. As was the case with
FIG. 1
, the silicon protrusion may impact yield and/or reliability of the integrated circuit device.
Other problems may also be created during fabrication of insulated electrodes.
FIG. 3
illustrates undercutting of an electrode insulating layer, such as a gate oxide layer.
Specifically, as shown in
FIG. 3
, an insulating layer such as an oxide layer
32
, a conductive layer such as a doped polysilicon layer
34
, a barrier metal layer
36
and a metal silicide layer
38
are formed on an integrated circuit substrate such as a silicon semiconductor substrate
30
, as was described above. A gate electrode
40
may be formed by etching the metal silicide layer
38
, barrier layer
36
and polysilicon layer
34
. When the barrier layer
36
is titanium nitride and the metal silicide layer is titanium silicide, an oxide layer
42
b
protruding from the sidewall of the barrier metal layer
36
may be formed when a gate oxidation process is performed. The oxide layer
32
may also be undercut.
Since the oxidation ratio of the barrier metal layer
36
may be higher than that of the polysilicon layer
34
or the metal silicide layer
38
, the oxide layer
42
b
on the sidewall of the barrier metal layer
36
may be thicker than the oxide layer
42
a
on the polysilicon layer
34
or on the metal silicide layer
38
. Accordingly, the lower edge portions
44
of the metal silicide layer
38
and the polysilicon layer
34
may become fragile. The undercutting of the oxide layer
32
, may also create reliability and/or performance problems for the integrated circuit.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide improved insulated electrode forming methods for integrated circuits, and insulated electrodes so formed.
It is another object of the present invention to provide insulated electrode forming methods that can prevent silicon protrusions in metal silicide layers, and insulated electrodes so formed.
It is another object of the present invention to provide insulated electrode forming methods that can reduce performance and/or reliability problems due to electrode insulator undercutting, and insulated electrodes so formed.
These and other objects are provided according to the invention by insulated electrode forming methods that first form on an integrated circuit substrate, an insulating layer, a conductive layer on the insulating layer, and a metal suicide layer on the conductive layer, and then form a metal silicon nitride layer on the metal silicide layer. The metal silicon nitride layer acts as a silicon protrusion-preventing layer on the metal silicide layer that prevents formation of silicon protrusions from the metal silicide layer during subsequent processing.
In a first embodiment of the present invention, the metal silicide layer includes an outer surface opposite the conductive layer. The metal silicon nitride layer is formed on the outer surface of the metal silicide layer, to prevent formation of silicon protrusions from the outer surface of the metal silicide layer during subsequent processing. In a second embodiment, the metal silicide layer includes a sidewall and the metal silicon nitride layer is formed on the sidewall of the metal silicide layer, to prevent formation of silicon protrusions from the sidewall of the metal silicide layer during subsequent processing. The metal silicon nitride layer may also be on both the outer surface and the sidewall of the metal silicide layer.
In the first embodiment, after forming a metal silicon nitride layer on the outer surface of the metal silicide layer, a selective etch of the metal silicon nitride layer, the metal silicide layer and the conductive layer is performed, to define an insulated electrode including a sidewall. A sidewall spacer is then

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