Integrated circuit including a test signal generator

Details Integrated circuit including a test signal generator Integrated circuit including a test signal generator

2000-12-26

2004-05-18

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S728000, C714S739000

Reexamination Certificate

active

06738940

ABSTRACT:

BACKGROUND OF THE INVENTION
The invention relates to the field of automatic testing of electronic components, and in particular to the field of testing integrated circuits.
Quality control of electric components and process control of production machines are extremely important in the production of integrated circuits, in order to assure that the components delivered by the manufacturer meet the requirements of the customer. Rational quality control of electric components includes not only testing of their electric properties, especially the access times of memory components, but also the checking for visible external defects. The electric properties of components are now being tested by automatic test equipment at the end of the production line.
The nature of the production process for electric components makes it impossible to guarantee 100% freedom from defects. After the production process, it is therefore necessary to test the component.
Testing techniques include measuring the analog characteristics of the finished electric component. It is also possible to apply digital test patterns to the terminals of the integrated circuit or of the electric component, and then to analyze the reactions.
The measurement of analog characteristics has the disadvantage that it is relatively time-consuming, if the digital signal processing unit in the integrated circuit configuration is to be tested. Adjustable components require a number of measurements with different settings. If an electric component actually has a defect, it is very difficult to localize this defect by measuring the analog characteristics.
The method of applying digital test patterns to the electric component and then analyzing the reaction of the component has the disadvantage that conventional test devices, so-called ASIC testers, operate synchronously with the electric component. As a result, an oscillator integrated within the integrated circuit that is being tested must be turned off or deactivated, because the test clock pulse is applied to a terminal of the integrated circuit.
Therefore, there is a need for improved testing of an integrated circuit, which quickly delivers a reliable test result to distinguish whether or not the integrated circuit is defective.
SUMMARY OF THE INVENTION
A pseudo-random-check generator inside a integrated circuit delivers a plurality of digital test data, each of which is processed in a digital signal processing device within the integrated circuit and which, after being processed are each conducted to a test sum calculator. The test sum calculator performs a polynomial calculation and adds up a test sum from the individual calculated results. The calculated test sum is used as the criterion for the absence of defects in the integrated circuit configuration. If the test sum deviates from the prescribed test sum, this indicates that the digital signal processing device in the integrated circuit configuration is defective.
To test the integrated circuit, a start command is applied to the integrated circuit causing a switch-over device inside the integrated circuit to connect a digital signal processing unit to-the pseudo-random-check generator. Then the digital signal processing unit is reset and the pseudo-random-check generator is started. Also, the test sum calculator preferably was previously reset to 0. The individual digital data delivered by the signal generator are processed in the digital signal processing unit, and the processed digital signal is conducted to the test sum calculator. This is done for every signal present at the output of the pseudo-random-check generator. After the pseudo-random-check generator has delivered a prescribed number of output data, it is stopped, and finally a test sum is made available at the output of the test sum calculator. This test sum is conducted, via an interface unit, to an output terminal of the integrated circuit configuration, and is there queried. Preferably it is queried by a protocol generator connected to a control computer. Finally, the switch-over device is again reset to normal operation.
In normal operation, an analog circuit section which can contain, for example, a sensor, especially a Hall sensor, is connected to the digital signal processing unit.
The advantages of this method is the relatively short measurement time which it needs to determine whether or not the integrated circuit is defective. The integrated circuit itself must include only few additional hardware components, mainly the switch-over device, the pseudo-random-check generator, and the test sum calculator, as well as the process control.
If the already existing terminals of the integrated circuit configuration are used as the signal input and output terminals for the test mode, this has the advantage that no additional terminals need to be furnished for the test mode. The reliability of the integrated circuit configuration is thus markedly improved, compared to other circuit configurations with several terminals.


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Agrawai et al. “Built-in self-test for digital integrated circuits”, AT&T Technical Journal, Mar.-Apr. 1994.

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