Integrated circuit having reduced probability of wire-bond failu

Details Integrated circuit having reduced probability of wire-bond failu Integrated circuit having reduced probability of wire-bond failu

1999-03-08

2000-11-28

Bowers, Charles

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438123, 438612, 438666, 257784, 257786, H01L 2144, H01L 2148, H01L 2150, H01L 2940

Patent

active

061535060

ABSTRACT:
The present invention provides an improved integrated circuit technique for increasing the reliability of wire-bonds in an integrated circuit by increasing the contact angle between certain pins and their respective wire-bonds, particularly those pins otherwise most susceptible to wire-bond failure, i.e., those pins conventionally located toward the corners of a conventional integrated circuit. By doing so, the overall length of the wire-bonds in a chip will be reduced, which in turn can result in further reduction of the probability of wire-bond failures. In a disclosed embodiment, a five or more sided integrated circuit shape is introduced wherein pads on up to four sides of an integrated circuit wafer chip are bonded to pins supported on eight edges of an integrated circuit package. An integrated circuit having at least five pin-supporting edges renders more robust wire-bond angles for any given integrated circuit package size.

REFERENCES:
patent: 5168368 (1992-12-01), Gow

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