Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Configuration or pattern of bonds
Reexamination Certificate
2006-05-16
2010-10-05
Mandala, Victor A (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Configuration or pattern of bonds
C257S782000, C257S602000, C257S700000, C257S758000, C257S774000, C257S775000, C257SE21590, C257SE23020, C257SE23037, C257SE23040, C257SE21523
Reexamination Certificate
active
07808117
ABSTRACT:
A pad (20) is electrically connected to a first I/O cell (14) while also physically overlying active circuitry of a second I/O cell (16). Note that although the pad (20) overlies the second I/O cell (16), the pad (20) is not electrically connected to the I/O cell (16). Such a pattern may be replicated in any desired manner so that the I/O cells (e.g.300-310) may have a finer pitch than the corresponding pads (320-324and330-335). In addition, the size of the pads may be increased (e.g. pad131may be bigger than pad130) while the width “c” of the I/O cells (132-135) does not have to be increased. Such a pattern (e.g.500) may be arranged so that the area required in one or more dimensions may be minimized.
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Carpenter Burton J.
Hong Dae Y.
Miller James W.
Phillips Kendall D.
Tran Tu-Anh N.
Chiu Joanna G.
Freescale Semiconductor Inc.
Hill Susan C.
Lopez Fei Fei Yeung
Mandala Victor A
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