Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-11-07
2004-06-29
Fahmy, Wael (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
Reexamination Certificate
active
06756642
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to integrated circuits, more particularly to MOS buffer drivers, and even more specifically to such circuits protected from electrostatic discharge (ESD).
2. Description of the Related Art
Electrostatic discharge (ESD) is a phenomenon, wherein static build-up, such as produced by friction, is applied to an object. When the object is an integrated circuit (IC), portions of the device can be permanently damaged. Another major source of ESD exposure to ICs is from the human body. A charge can be induced on a body capacitance of 150 picofarads, leading to electrostatic potentials of 4 kV or greater. Contact with a charged human body by an uncharged or grounded IC pin can result in a discharge for about 100 ns with the currents of several amperes. Similar levels of ESD may be imposed on IC's from other sources such as metallic objects and the so-called charged device model (CDM) wherein the IC itself is charged and discharged to ground. Since ESD can involve pulses of thousands of volts, the damage can be surprisingly high.
The above actions usually destroy the IC. However, at lower ESD levels, PN junctions can be degraded so that leakage currents can increase to an unacceptable level. Accordingly, the ESD limits are related to acceptable performance levels. With respect to what can happen when damage occurs, several failure mechanisms can develop. The discharge energy can melt the silicon, into which the IC is fabricated. It can also rupture the silicon dioxide insulation. Here it is most likely that a metal oxide semiconductor (MOS) transistor gate oxide rupture will occur first because this oxide is the thinnest in the IC. Further, it can cause fusion of the interconnect metal or evaporate polysilicon conductors.
In testing the tolerance of an IC to ESD, it is common to charge a 150 pF capacitor to a controlled variable voltage (typically 1 to 2 kV) and then connect it through a 1.5 k&OHgr; resistor to the various pins of the IC. The signal input/output pins are typically the most sensitive to damage from ESD. The capacitor charge is incremented until damage occurs and the level noted. The ESD resistance can then be rated in terms of the highest value of charge voltage that the IC can withstand without harm.
As the density of very large scale integrated circuits (VLSI) increases, the components of the circuits are becoming progressively smaller and more susceptible to damage from ESD. For example, the gate oxides of MOS transistors are becoming thinner and thinner, thus making oxide layer more susceptible for destruction caused by ESD. During an ESD event, charge is transferred between one or more pins of the IC and another conducting object in a time period that is typically less than one microsecond. This charge transfer can develop voltages that are large enough to break down insulating films (e.g., gate oxides) on the device, or can dissipate sufficient energy to cause electrothermal failures in the device. Such failures include contact spiking, silicon melting, or metal interconnect melting. It is especially important to protect gate oxide at input buffers and MOS components at bi-directional buffers and output drivers.
Therefore, the protection of ICs from ESD has received much attention from circuit designers. Workers in the field and inventors have proposed a lot of solutions, many trying to solve the problem of protecting sub-micron devices while still allowing them to function unencumbered and without undue, or zero, increase of silicon real estate. The resulting protection circuits may typically be connected to all Input/Output (I/O) pads of an integrated circuit (IC) to safely dissipate the energy associated with ESD events without causing any damage to the circuitry internal to the device. Protection circuits have also been connected to power supply pads, or between power supply buses to prevent such damage to internal circuits. In developing effective ESD protection circuitry, circuit designers may be limited with regard to the particular structures used, inasmuch as the protection circuit so designed must integrate well with the remainder of the integrated circuit. That is, the protection circuit must not interfere with meeting chip-level parameters.
One such parameter of interest is known as an input “leakage” current parameter. This parameter is particularly important where the input pins of the integrated circuit are subjected (either by design or accidentally) to voltages, which exceed the positive power supply voltage of the integrated circuit. For example, particular integrated circuits may be contemplated for use in a mixed-voltage environment, where the integrated circuit may operate at one voltage level (e.g., V
DD
=3.3 volts), but must interface with another integrated circuit operating at a different, higher power supply voltage (e.g. 5.0 volts). As another example, the particular integrated circuit may be required to have a “hot-socket insertion” capability (i.e., the destination system is not powered down prior to insertion of the integrated circuit). In these “hot-socket” insertion situations, the time order of voltages applied to the various pins of the IC cannot be controlled.
Another solution to this problem, incorporating an on-chip ESD protection circuit on the input/output (I/O) pads of CMOS (complementary metal-oxide semiconductor) devices, comprises an ESD protection circuit connected to an input pad (IP). The circuit includes a field oxide device (FOD), an NMOS (N-type metal-oxide semiconductor) transistor, a resistor connected between them, and an inverter at the input of the circuit to be protected. The NMOS transistor is connected in such a manner that its gate is connected to the ground power line (thus referred to as a gate-grounded NMOS transistor) and is specifically designed to operate in the breakdown mode.
When an ESD stress appears at the IP, the resulting ESD current can bypass through the gate-grounded NMOS transistor to the ground power line. To allow the transistor to provide this ESD protection effect, the breakdown voltage of this transistor should be smaller than the breakdown voltage of the gate oxide layer in the inverter. The breakdown voltage of the gate-grounded NMOS transistor decreases as the channel length is shortened. However, a short channel length will make the transistor undesirably more vulnerable to ESD stress. The provision of the resistor can suppress the ESD current flowing through the gate-grounded NMOS transistor. Moreover, the FOD can help drain part of the ESD current from the IP to the ground power line. The FOD is preferably constructed on a non-lightly doped drain (LDD) structure, which allows it to be longer in channel length than the gate-grounded NMOS transistor so as to be capable of withstanding larger ESD currents.
A negative ESD voltage applied to the IP causes the gate-grounded NMOS transistor to produce a parasitic diode current. A positive ESD voltage applied to the IP causes the gate-grounded NMOS transistor to produce an NPN avalanche breakdown current, thus causing a large potential drop across the resistor. As a result of this, the FOD is switched to the conductive state. If the FOD is designed to be longer in channel length than the gate-grounded NMOS transistor, it will be also larger in breakdown voltage than the gate-grounded NMOS transistor. Therefore, the level of the breakdown voltage of the FOD can be close or even larger than that of the gate oxide layer in the inverter. If the IC device is further downsized, the gate oxide layer in the inverter will be correspondingly made thinner. As a result, the inverter would be subjected to a breakdown voltage before the NPN or PNP conduction takes place in the ESD protection circuit. The ESD protection circuit is therefore reduced in its ESD robustness to provide adequate ESD protection to the downsized IC device. Thus, as semiconductor fabrication technologies have advanced to the deep-submicron level, the conventional ESD protect
Chen Shui-Hung
Lee Jian-Hsing
Yu Ta-Lee
Fahmy Wael
Farahani Dana
Taiwan SEmiconductor Manufacturing Co., Ltd
Tung & Associates
LandOfFree
Integrated circuit having improved ESD protection does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated circuit having improved ESD protection, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit having improved ESD protection will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3352690