Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-03-22
2003-10-28
Baker, Stephen M. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S730000
Reexamination Certificate
active
06640322
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuits, and more particularly to integrated circuits including control and status registers.
2. Description of the Related Art
A typical computer system includes a central processing unit (CPU) coupled to one or more peripheral devices (e.g., disk drives and printers). The CPU typically monitors and controls the peripheral devices via addressable control and status registers (CSRs) within the devices. For example, in order to determine the state of a peripheral device, the CPU may read a status value from an address of a status register within the device. In order to configure or control functions of the device, the CPU may write a control value to an address assigned to a control register within the device. It is noted that the CPU itself may include CSRs, and may be monitored and controlled via the CSRs.
The CSRs of a device are typically formed with other device logic upon a single integrated circuit (IC). As IC fabrication technology has improved, the ability to integrate more and more functions onto single silicon substrates has increased. As a result, the number of functions performed by devices has also increased. In turn, the number of CSRs within the devices has necessarily increased. In fact, some devices now include hundreds of CSRs. It is also noted that shrinking IC device geometries have also allowed operating speeds of devices to increase.
FIG. 1
is a diagram of a representative integrated circuit (IC)
10
forming a device and including a centralized control and status register (CSR) block
12
. CSR block
12
includes a set of addressable CSRs
16
assigned to the device. CSR block
12
is coupled to a set of input/output (I/O) pads
14
and to each of five functional units, numbered
1
through
5
, dispersed about a surface of a semiconductor substrate
15
. Each of the five functional units performs one or more logical functions dependent upon control values stored in control registers of CSR block
12
. I/O pads
14
are adapted to receive address, data, and control signals from, for example, signal lines of an external bus coupled to I/O pads
14
. When a write command conveyed via the address, data, and control signals includes an address of one of the CSRs
16
, CSR block
12
stores the data within the addressed CSR. When a read command conveyed via the address, data, and control signals includes an address of one of the CSRs
16
, CSR block
12
drives a data portion of I/O pads
14
with data stored within the addressed CSR.
CSR block
12
distributes control signals stored within control registers of the CSRs
16
to the five functional units via some signal lines of the multiple buses
18
, and receives status information to be stored in the status registers of CSRs
16
via other signal lines of the multiple buses
18
. As each bus
18
may have hundreds of signal lines, the routing of the signals lines of the multiple buses
18
across the substrate becomes a problem when IC
10
has a relatively large number of functional units. In addition, where IC
10
operates at high speeds (i.e., high clock frequencies), the fact that signals driven upon the signal lines of the multiple buses
18
in unison may not reach their destinations simultaneously creates signal timing problems.
It would thus be desirable to position CSRs of an integrated circuit and to route signals to the CSRs in a manner which reduces the signal routing and timing problems typical of current integrated circuits.
SUMMARY OF THE INVENTION
An integrated circuit is presented having a plurality of logic modules dispersed about a surface of a semiconductor substrate. Each logic module includes a set of control and status registers including at least one control register storing a control value. A functional unit of each logic module performs one or more logic functions dependent upon the control value stored in the control register. A central controller is coupled to each of the logic modules. The central controller is adapted to receive address, data, and control signals (e.g., from signal lines of an external bus coupled to I/O pads of the integrated circuit), and issues read and write commands to the control and status registers dependent upon the address, data, and control signals. A write command may, for example, modify the control value stored in a selected one of the control registers.
The functional unit of each logic unit may generate a status value during operation, wherein the status value reflects a status of the functional unit. A status register of the corresponding set of control and status registers may store the status value. The central controller may issue a read command to obtain the status value stored in a selected one of the status registers, and may drive the I/O pads of the integrated circuit with the status value.
The integrated circuit may include a bus which couples the central controller to each of the logic modules. The bus may, for example, couple the central controller and each of the logic modules in series forming a communication ring. In this case, the central controller and the logic modules represent separate modules along the communication ring which communicate by exchanging data via the communication ring. The data may travel in a single direction around the communication ring. The central controller and the logic modules may communicate according to an established set of communication rules.
The central controller and the logic modules may exchange packetized data. A given packet may include an address payload and/or a data payload. The address payload may include packet type (e.g., command) information. The address payload may also include a module identification value which uniquely identifies the module to which the packet is directed. The address payload may also include information which identifies a control or status register to which a command is directed. For example, the address payload of a packet may include information identifying the packet as conveying a write command, may include information identifying the module to which the packet is directed, and may also include information identifying the control register to which the write command is directed. The data payload may include read data or write data. Packets may also include error checking information such as a cyclic redundancy check (CRC) value.
Each logic module may also include a distributed controller coupled to the control and status registers. The distributed controller may receive commands and access control or status registers in response to the commands. The central controller may be coupled to the distributed controller of each of the logic modules via the above described bus. The central controller may issue the read and write commands to the distributed controllers, and the distributed controllers may carry out the read and write commands. For example, in response to a write command received from the central controller and directed to a control register, a distributed controller may modify a control value stored in the control register.
The central controller may also manage error logging and reporting for the distributed control and status registers. An error packet transmitted by a module detecting an error may have a data payload including a time stamp. The time stamp may be, for example, the value of a free running counter within the distributed controller of the reporting module when the error was detected. The free running counter value within error packets allows the central controller to determine which module detected an error first. Such information may help to determine where a fault exists.
REFERENCES:
patent: 4701921 (1987-10-01), Powell et al.
patent: 4918379 (1990-04-01), Jongepier
patent: 5477548 (1995-12-01), Beenker et al.
patent: 5577052 (1996-11-01), Morris
patent: 5983301 (1999-11-01), Baker et al.
patent: 6065078 (2000-05-01), Falik et al.
patent: RE36839 (2000-08-01), Simmons et al.
patent: 6115763 (2000-09-01), Douskey et al.
patent: 6202163 (20
Baker Stephen M.
Kivlin B Noël
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Sun Microsystems Inc.
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