Integrated circuit having an interlevel interconnect coupled to

Details Integrated circuit having an interlevel interconnect coupled to Integrated circuit having an interlevel interconnect coupled to

1998-05-06

2000-11-14

Monin, Jr., Donald L.

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Recessed oxide by localized oxidation

438586, 438664, 438233, 257382, 257383, 257384, H01L 218238, H01L 31119, H01L 214763, H01L 2144

Patent

active

061469785

ABSTRACT:
An interlevel interconnect is formed in a window opened through an isolation layer and through an etch barrier to expose an electrode surface and an adjacent isolation barrier. The interlevel interconnect may be disposed on substantially all of a portion of the underlying electrode such as an insulated gate field effect transistor (IGFET) source/drain region surface. The etch barrier provides controlled etching to allow for overlap of the interlevel interconnect onto the isolation barrier without increased parasitic capacitance relative to conventional contact misalignments. Furthermore, allaying concerns of overlapping allows for increased utilization of source/drain region surface area by the interlevel interconnect. Furthermore, the etch barrier allows the interlevel interconnect to strap electrodes of a plurality of circuit devices while exhibiting nominal if any substrate to interlevel interconnect leakage currents.

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Stanley Wolf, Ph.D.; Silicon Processing for the VLSI Era, vol. 2: Process Integration; Published by Lattice Press, Sunset Beach CA; 1990; pp. 162-174, 178-179, and 190-191.

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