Narrow data width DRAM with low latency page-hit operations

Details Narrow data width DRAM with low latency page-hit operations Narrow data width DRAM with low latency page-hit operations

1997-10-02

1999-10-19

Nguyen, Viet Q.

Static information storage and retrieval

Read/write circuit

Multiplexing

36518905, 36523002, 36518903, 36518901, G11C 1500

Patent

active

059699973

ABSTRACT:
A high speed Random Access Memory (RAM) array device includes several logical banks, each of which can be uniquely addressed. Each of these logical banks contains a unique memory array segment and associated page register, the latter serving as a temporary storage location during high-speed page hit operations. To reduce latency during an initial page hit, further array optimization is realized by segmenting each logical bank into two segments with one, smaller segment, comprising a faster random access memory (FRAM) for storing initial data in a data stream. A high speed page register connects the FRAM directly to a multiplexer/demultiplexer connected to the device I/O ports bypassing an internal bus protocol such that the initial data can be transferred between the FRAM and the I/O ports faster thereby improving page-hit latency. Hence, segmenting the logical banks to include only a small high speed segment results in a performance gain approaching what could be achieved by implementing the entire memory device with a high speed FRAM, but at much lower cost.

REFERENCES:
patent: 5283880 (1994-02-01), Marcias-Garza
patent: 5289584 (1994-02-01), Thome et al.
patent: 5737563 (1998-04-01), Shigeeda
patent: 5793663 (1998-08-01), Ng et al.
patent: 5805854 (1998-09-01), Shigeeda

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