Integrated circuit having a top side wafer contact and a...

Details Integrated circuit having a top side wafer contact and a... Integrated circuit having a top side wafer contact and a...

2008-01-18

2010-06-22

Smith, Matthew (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C257SE21575

Reexamination Certificate

active

07741205

ABSTRACT:
The present invention provides an integrated circuit and a method of manufacture therefore therefor. The integrated circuit (100, 1000), in one embodiment without limitation, includes a dielectric layer (120, 1020) located over a wafer substrate (110, 1010), and a semiconductor substrate (130, 1030) located over the dielectric layer (120, 1020), the semiconductor substrate (130, 1030) having one or more transistor devices (140, 1040) located therein or thereon. The integrated circuit (100, 1000) may further include an interconnect (170, 1810) extending entirely through the semiconductor substrate (130, 1030) and the dielectric layer (120, 1020), thereby electrically contacting the wafer substrate (110, 1010).

REFERENCES:
patent: 5940705 (1999-08-01), Lee et al.
patent: 6429099 (2002-08-01), Christensen et al.
patent: 6613834 (2003-09-01), Nakata et al.
patent: 7199050 (2007-04-01), Hiatt
patent: 7262109 (2007-08-01), Lin et al.
patent: 7465639 (2008-12-01), Pelella et al.

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