Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-09-08
2002-07-02
Chung, Phung M. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S731000
Reexamination Certificate
active
06415401
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims priority from prior French Patent Application No. 98-11384, filed Sep. 8, 1998, the entire disclosure of which is herein incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to electronic circuits, and more specifically to an integrated circuit having a test cell that resynchronizes the integrated circuit.
2. Description of Related Art
FIG. 1
shows a synchronous integrated circuit
10
. This integrated circuit
10
may be considered to be a functional electronic circuit with data inputs I
1
to In, a clock input CK, and data outputs S
1
to Sn.
FIG. 2
shows another integrated circuit
20
that is similar to the integrated circuit
10
of
FIG. 1
, but with test means on the external connections. The test means of the integrated circuit
20
includes test cells
21
that are associated with each input and output. The test cells are connected to each other and form a shift register that is accessible through a test input DI, a test output DO, and a control bus Ctrl. The many possible embodiments of this type of test circuit include a test device according to IEEE standard 1149.1.
The development of technologies in the field of integrated circuits is providing for increasingly large-scale integration. It is common today to design integrated circuits in which there are assembled circuits that are already made in the form of smaller-sized integrated circuits. In order to reduce development costs, there are conventional ways of re-utilizing pre-designed integrated circuits.
FIG. 3
shows an integrated circuit
30
containing a group of three circuits IP
1
, IP
2
, and IP
3
that were developed independently. Each circuit IP
1
to IP
3
may have inputs and/or outputs and possibly inputs and/or outputs connected with the other circuits IP
1
to IP
3
and possibly inputs and/or outputs for external communications. The clock inputs of the different circuits IP
1
to IP
3
are grouped together to receive the same clock signal.
It is possible to have a test path on such an assembly of circuits as shown in FIG.
4
. The integrated circuit
40
of
FIG. 4
has three circuits IP
1
to IP
3
each including test cells
41
that are linked with test cells
42
of the integrated circuit
40
. It is not necessary to have two test cells
41
or
42
on the same conductor unless the integrity of the conductor has to be tested. Thus, if the inputs and/or outputs of the circuits IP
1
to IP
3
are in the vicinity of the inputs and/or outputs of the integrated circuit
40
, then it is unnecessary to add test cells
42
for those inputs and/or outputs. By contrast, the use of test cells
41
on the internal connections enables the testing of the connections between the circuits IP
1
to IP
3
.
It is also possible to have a duplicated test path. For example, a first test path can be formed by the test cells
42
, and a second internal test path can be formed by the test cells
41
. The first and second test paths may both be externally accessible through multiplexing depending on what is to be tested. The testing of the internal connections is above all useful to the manufacturer of integrated circuits.
FIG. 5
shows a conventional test cell
50
meeting the specifications of IEEE standard 1149.1. This cell
50
is a one-way cell and can be used on an input or an output, depending on the direction in which it is placed. There are also many conventional variants. While
FIGS. 1
to
4
refer only to circuits having dedicated inputs and outputs, in practice there are many circuits having two-way inputs/outputs. The present invention does not specifically address inputs/outputs because these may be considered to be paired combinations of inputs and outputs.
FIG. 6
shows a conventional example of the use of a test cell
50
on a two-way bus, with duplicated data corresponding to the internal part of the circuit. Thus, it is possible to consider only dedicated inputs and outputs.
One problem that the present invention seeks to resolve pertains to the bringing together of conventional integrated circuits in the same integrated circuit (as shown in FIGS.
3
and
4
), with each of the circuits IP
1
to IP
3
being made independently. The resultant integrated circuit
30
or
40
is an assembly of conventional circuits. During the designing of the resultant circuit
40
, the circuits IP
1
to IP
3
are modified to the minimum extent, or not even modified at all.
The problem of synchronization between circuits then arises because each circuit IP
1
to IP
3
works with an internal clock signal H
1
to H
3
that is different from the others. This arises out of the synchronization of the circuit IP
1
to IP
3
which is done autonomously. It is vitally important in an integrated circuit that all the clock signal edges should be simultaneous on all the circuits that use the clock signal. The use of a clock signal distribution circuit almost automatically leads to a phenomenon of general latency on the totality of the integrated circuit in order to compensate for the phase differences appearing on the clock signal at the inputs of the different circuits.
Thus, when several circuits IP
1
to IP
3
that have been designed as independent integrated circuits are integrated into one integrated circuit
40
by making a simple connection of the clock inputs of the different circuits IP
1
to IP
3
with the clock input of the integrated circuit, then the internal clock signals H
1
to H
3
shown in
FIGS. 7B
to
7
D are obtained. It can be seen in
FIGS. 7A
to
7
D that each clock signal H
1
to H
3
has a phase delay &dgr;
1
to &dgr;
3
with respect to the clock signal at the clock input CK. It is possible to have, for example, &dgr;
1
=5 ns, &dgr;
2
=7 ns, and &dgr;
3
=3 ns. This illustrative example considers a data element present in a register of the circuit IP
1
which, during a clock signal edge, will be replaced by a data element Di+1, the output of the register of the circuit IP
1
corresponding to an output of the circuit IP
1
.
If the output of the circuit IP
1
is connected to an input of the circuit IP
2
, then depending on the size of the phase shift between clock signals H
1
and H
2
, and depending on the conduction lengths between the circuits IP
1
and IP
2
, and depending on the presence, if any, of logic gates at the input of a synchronous circuit of the circuit IP
2
, it is possible to load either the subsequent data element Di or the data element Di+1, or even an indeterminate state that corresponds to the transition between the data elements Di and Di+1, in the synchronous circuit of the circuit IP
2
. This results in an uncertainty about the degree of correct operation of the circuit IP
2
. If the output of the circuit IP
1
is connected to an input of the register of the circuit IP
3
, then the data element Di is loaded into the register of IP
3
during an edge corresponding to the edge used for the loading of the data element Di+1 into the register of the first IP
1
.
A first solution to such problems consists in resynchronizing the clock signals H
1
to H
3
by delaying the clock signals given to each circuit in varying degrees. However, during a clock resynchronization operation, it should be possible to tolerate a margin of error that is a function of the different parameters of an integrated circuit (e.g., temperature, supply voltage, positioning in the integrated circuit, and technology). Conventionally, this margin of error is such that it corresponds to about the minimum time of propagation of a logic gate (i.e., approximately 0.1 to 0.2 ns for a 0.35 &mgr;m technology) so as to have no effect on the circuits.
The problem with this approach is that the individual circuits IP
1
to IP
3
are designed with synchronized clock circuits that already use this same margin of error. If the resynchronization of the clock signal is simply done at the input of each circuit IP
1
to IP
3
, then the margin of error is
Bongini Stephen
Chung Phung M.
Fleit Kain Gibbons Gutman & Bongini P.L.
Jorgenson Lisa K.
STMicroelectronics S.A.
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