Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-04-05
2010-10-05
Chung, Phung M (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S724000, C714S726000, C714S763000, C714S807000
Reexamination Certificate
active
07810004
ABSTRACT:
An integrated circuit having a subordinate test interface and method for transmitting digital data is disclosed. The integrated circuit includes at least one test interface that is adapted to write and read data in and from a data memory, the at least one test interface includes, for transmitting and receiving data of different content categories, one signal line each for every content category. The integrated circuit further includes an interface module for receiving and transmitting data, and that the interface module is, via the signal lines, connected with the test interface for transmitting the data of the different content categories.
REFERENCES:
patent: 6088822 (2000-07-01), Warren
patent: 6381721 (2002-04-01), Warren
patent: 6823282 (2004-11-01), Snyder
patent: 7099963 (2006-08-01), Byers et al.
patent: 2001/0034598 (2001-10-01), Swoboda
patent: 2004/0001432 (2004-01-01), Wescott
Mayer Albrecht
Siebert Harry
Chung Phung M
Dicke Billig & Czaja, PLLC
Infineon - Technologies AG
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