Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-08-04
2002-07-02
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S030000, C714S034000
Reexamination Certificate
active
06415406
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to an integrated circuit having a self-test device and a method for producing the integrated circuit.
U.S. Pat. No. 5,173,906 to Dreibelbis et al. describes an integrated circuit having a self-test device (built-in self-test). In a test-operating mode, the self-test device carries out a test of specific circuit components of the integrated circuit. At the same time, it carries out a desired/actual comparison of signals generated by the circuit unit to be tested. The self-test device records errors during the test. After the test concludes, the self-test device passes one or more result signals to a point outside the integrated circuit, the result signals specifying the extent to which errors have occurred during self-test implementation.
A self-test device may be realized either through wired logic, a programmable logic unit, or a controller, which in each case executes test programs that can be loaded into a program memory of the integrated circuit. In the last of the three mentioned cases, the self-test device processes a test program situated in the program memory command by command, without the ability to influence the program flow.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an integrated circuit having a self test device and a method for producing a self-testing integrated circuit, which overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type and which permits an integrated circuit with a self-test device and a program memory to store an externally loadable test program for the self-test device, whereby it is possible to influence the test program flow.
With the foregoing and other objects in view, there is provided, in accordance with the invention, an integrated circuit, including at least one external terminal, a program memory connected to the at least one external terminal for loading external test programs into the program memory, and a self-test device connected to the program memory and having an input for an interrupt signal, the self-test device executing program commands of the external test program loaded into the program memory to carry out a self-test of the integrated circuit, the program commands succeeding one another in address terms, the self-test device, upon receiving the interrupt signal, interrupting an execution of the external test program by executing a program jump in address terms within the external test program instead of executing the respective succeeding program command of the external test program.
The integrated circuit of the invention is distinguished by the fact that its self-test device has an input for an interrupt signal, through which the self-test device interrupts the test program currently being executed by not executing the respective succeeding program command of the test program in address terms. Rather, it executes a program jump within the test program, the program jump being triggered by the interrupt signal.
Providing an interrupt possibility by the self-test device during the execution of a test program advantageously makes it possible to influence the course of the test. The interrupt signal can either be generated on-chip or be fed to the integrated circuit externally. Allowing for program flow influencing, for example, by either an integrated circuit operator or an external test device. Also for example, an integrated circuit operator can trigger the interrupt dependent upon specific operating states and/or specific signals generated on the integrated circuit. The invention is suitable for application in any kind of integrated circuit, for example, in logic or memory circuits.
Memory cells of dynamic memory circuits (DRAMs) are usually realized as single-transistor memory cells. Due to leakage current of their storage capacitor, it is necessary to regularly refresh the stored information. The act is referred to as refresh.
In accordance with a further feature of the invention, the integrated circuit is a dynamic memory circuit having memory cells, in which the interrupt signal triggers a program jump to program commands, upon execution thereof, the self-test device carries out a memory cell content refresh. The development affords the advantage of eliminating the need for providing memory cell refresh through additional devices because the self-test device itself carries out the refresh. Co-ordination between the respective test program to be executed and refresh is temporarily optimized because of the self-test device carrying out the refresh. The result is particularly expedient if the self-test device tests the memory cells in the context of the test program. The memory cells are then both tested and refreshed by the self-test device.
In accordance with an added feature of the invention, there is provided a time measuring device for generating the interrupt signal. The invention can then be dimensioned advantageously so that the interrupt signal is generated at desired, regular time intervals. The configuration makes the invention particularly suitable for generating the interrupt signal for the self-test device to trigger refresh. As is known, refresh is cyclically repeated.
If necessary, the interrupt signal can, inter alia, also be used for prematurely ending the test program currently being processed by the self-test device. In addition, it can be used for interrupting the test program currently being executed, initializing the self-test device and subsequently beginning the processing of the program anew at the program start.
In accordance with an additional feature of the invention, there is provided a second external terminal for supplying the interrupt signal, the interrupt signal originating from outside the integrated circuit.
With the objects of the invention in view, there is also provided a method of producing a self-testing integrated circuit, the method including the steps of providing a self-test device, a program memory and an external terminal, connecting the self-test device to the program memory, connecting the program memory to the external terminal, loading external test programs having programs commands into the program memory through the external terminal, running the external test program and executing the program commands to carry out a self-test of the integrated circuit, the program commands succeeding one another in address terms, generating an interrupt signal and inputting the interrupt signal into the self-test device, interrupting execution of the external test program being executed by the self-test device by executing a program jump in address terms within the external test program instead of executing the respective succeeding program command of the external test program, the program jump being triggered by the interrupt signal.
In accordance with a further mode of the invention, there is provided the step of subsequently executing the respective succeeding program command of the external test program after the program commands for carrying out a self-test of the integrated circuit are complete.
In accordance with an added mode of the invention, there is provided the step of providing a dynamic memory circuit having memory cells, with the step of executing the program commands including triggering a program jump to execute a memory cell refresh through the program commands.
In accordance with an additional mode of the invention, the step of generating the interrupt signal including generating the interrupt signal by a time measuring device.
In accordance with a concomitant mode of the invention, there is provided the steps of providing a further external terminal and feeding the interrupt signal from outside the integrated circuit through the further external terminal.
Other features that are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated circuit having a self-test device and a method for producing
Kaiser Robert
Krasser Hans-Jürgen
Schamberger Florian
De'cady Albert
Greenberg Laurence A.
Mayback Gregory L.
Siemens Aktiengesellschaft
Stemer Werner H.
LandOfFree
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