Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Decoding
Reexamination Certificate
1999-12-22
2001-07-03
Wamsley, Patrick (Department: 2819)
Electronic digital logic circuitry
Function of and, or, nand, nor, or not
Decoding
C326S035000, C365S230060
Reexamination Certificate
active
06255855
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to an integrated circuit having a decoder for generating an output signal with any one of three different potentials at an output terminal.
2. Summary of the Invention
It is accordingly an object of the invention to provide an integrated circuit having a decoder that generates an output signal with three different potentials as a function of input signals.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated circuit that includes a decoder having an output terminal, a first terminal, a second terminal, a third terminal, a fourth terminal, and a fifth terminal. The decoder has three operating states including a first operating state for generating a first potential at the output terminal, a second operating state for generating a second potential at the output terminal, and a third operating state for generating a third potential at the output terminal. The second potential lies between the first potential and the third potential. The decoder also includes a first transistor being of a first conductivity type, having a control terminal connected to the third terminal of the decoder and having a drain-to-source path. The decoder includes a second transistor being of a second conductivity type, having a control terminal connected to the fourth terminal of the decoder and having a drain-to-source path. The decoder includes a third transistor being of the second conductivity type, having a control terminal connected to the fifth terminal of the decoder. The decoder includes a fourth transistor having a control terminal connected to the fourth terminal of the decoder and having a drain-to-source path for connecting the output terminal of the decoder to the second potential. The decoder includes a series circuit connected between the first terminal of the decoder and the second terminal of the decoder. The series circuit includes the first transistor, the second transistor, the third transistor, and a node connected to the output terminal of the decoder and between the first transistor and the second transistor. The integrated circuit, with its first decoder, enables the generation of three different potentials as a function of signals present at the five terminals of the decoder.
In accordance with another feature of the invention, the decoder has a fifth transistor of the second conduction type, which connects the output terminal to the fourth transistor. Consequently, the output terminal is connected to the second potential through a series circuit formed by the fifth and fourth transistors. A control terminal of the fifth transistor is connected to a fixed potential lying between the second and the third potential. This provides the advantage that the bulk terminal of the fourth transistor can be connected to the fixed potential even when the third potential is present at the output terminal of the decoder, since the fourth transistor is not connected directly to the output terminal. The fourth transistor is connected to the output terminal through the fifth transistor. Consequently, the magnitude of the gate-bulk voltage and of the gate-drain voltage of the fourth transistor is limited, as a result of which the gate oxide of the fourth transistor is exposed to relatively low loading. Therefore, the lifetime of the fourth transistor is longer than if the fifth transistor were not present.
In accordance with an added feature of the invention, the integrated circuit has a control circuit that is connected to the five terminals of the decoder. The control circuit has a plurality of operating states in which it generates potentials at the five terminals of the decoder. The decoder generates one of the three different potentials at the output terminal, as a function of the potentials at the five terminals of the decoder.
In accordance with an additional feature of the invention, the control circuit has an inverter configured between the third and the fourth terminal. In this case, the third terminal may be the input and the fourth terminal may be the output of the inverter, or vice versa. Consequently, the control circuit enables the potential at one of these two terminals to be obtained from the potential at the other one of the terminals in a simple manner. It is also possible for the inverter to be a level converter, with the result that level conversion takes place in addition to the inversion.
In accordance with a further feature of the invention, as an alternative to or in addition to the inverter, the control circuit has another inverter configured between the first and the fifth terminal. The first or the fifth terminal may be the input of the second inverter, and the other one of the first and fifth terminals may be the output. This inverter may also have a level converter.
In accordance with an another added feature of the invention, the integrated circuit has another decoder constructed like the decoder. The two decoders may advantageously form a first decoder group, in which the third and the fourth terminals of the decoders are connected to one another. This enables joint driving of the decoders of the first decoder group through the interconnected third and fourth terminals. The potentials at the first, second and fifth terminals of the two decoders are controlled independently of one another.
In accordance with a concomitant feature of the invention, the integrated circuit has a second decoder group constructed like the first decoder group. The first, the second and the fifth terminals of corresponding decoders of the two decoder groups are connected to one another. The third and fourth terminals of each decoder within a respective decoder group are connected to one another. The overall result being that a configuration is produced which can be driven with comparatively little complexity.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated circuit having a decoder, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
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Bohm Thomas
Braun Georg
Honigschmid Heinz
Manyoki Zoltan
Rohr Thomas
Cho James H
Greenberg Laurence A.
Infineon - Technologies AG
Lerner Herbert L.
Stemer Werner H.
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