Integrated circuit for writing, reading and erasing memory matri

Details Integrated circuit for writing, reading and erasing memory matri Integrated circuit for writing, reading and erasing memory matri

1982-03-18

1985-01-08

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365182, G11C 1140

Patent

active

044930585

ABSTRACT:
A memory access and control circuit is described for use with a non-volatile memory matrix utilizing insulated gate field effect transistors. Two one out of n selector circuits which are complementary in operation and which are formed from transistors of opposite conductivity type are formed on an integrated circuit and transistors of one conductivity type are formed in insulating islands in the substrate.

REFERENCES:
patent: 4228527 (1980-10-01), Gerber et al.
patent: 4330850 (1982-05-01), Jacobs et al.

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