Integrated circuit for clock generation for memory devices

Details Integrated circuit for clock generation for memory devices Integrated circuit for clock generation for memory devices

2008-04-28

2010-02-23

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S154000, C365S189110, C365S233100

Reexamination Certificate

active

07668022

ABSTRACT:
A device for generating clock signals for use with a plurality of DDR memory devices on a dual in-line memory module (DIMM) board is provided that has a data buffer for buffering data. A clock divider divides a first clock signal (CLK1) having a first clock frequency to generate a second clock signal (CLK20) having a second clock frequency which is an integer multiple of the first clock frequency. A shift register (SH) receives the second clock signal as a data input signal, and comprises a plurality flip-flops having clock inputs coupled to receive the first clock signal (CLK1), and further coupled so that the data output of a preceding flip-flop is coupled to be the data input of a following flip-flop. The second clock signal is shifted through the shift register (SH) in response to the first clock signal (CLK1) to generate a plurality of shifted clock signals (CLK21, . . . , CLK32) at respective data outputs of the plurality of flip-flops. A multiplexer commonly coupled to the data outputs of the flip-flops selects one of the shifted clock signals (CLK21, . . . , CLK32) to serve as an output clock signal for transmission of the buffered data to a memory device.

REFERENCES:
patent: 5909247 (1999-06-01), Hosokai et al.
patent: 2002/0015338 (2002-02-01), Lee
patent: 2002/0172079 (2002-11-01), Hargis et al.
patent: 2005/0218956 (2005-10-01), LaBerge
patent: 2007/0002641 (2007-01-01), Kim et al.

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