Integrated circuit fault insertion system

Details Integrated circuit fault insertion system Integrated circuit fault insertion system

2001-06-25

2004-10-12

Lamarre, Guy J. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S030000, C716S030000

Reexamination Certificate

active

06804801

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to fault insertion in an integrated circuit, and more particularly to fault insertion for the purpose of testing diagnostic software.
BACKGROUND OF THE INVENTION
The traditional goal of circuit level testing is to determine that all components on a printed circuit board assembly (PCBA) are functioning properly. This testing is typically performed at the manufacturing level so as to detect defects at the earliest stage, and is performed while the PCBA is in a non-functional state. The testing is accomplished by applying a set of test input signals at various nodes on the PCBA and reading a resulting set of test output signals. It can be determined if the PCBA components are functioning properly by comparing the actual test output signals with the expected set of test output signals.
For PCBAs having a low level of integration, most nodes of the PCBA are externally accessible, and testing can be accomplished by, for example, a “bed of nails” test jig. As PCBAs become increasingly more complex in their use of integrated circuits and surface mount interconnection technology, more of the nodes and circuits of the PCBA become externally inaccessible, or hidden. In highly integrated circuits, such as field programmable gate arrays (FPGAs), programmable logic devices (PLDs), large scale, very large scale and ultra large scale integration (LSI/VLSI/ULSI), and application specific integrated circuits (ASICs), different designs for testability and testing methodologies are required.
A well known and common manufacturing design technique allowing for easier testing of highly integrated circuits is the “boundary-scan” technique, as described in the Institute of Electrical and Electronic Engineers (IEEE) standards document IEEE Std 1149.1-1990, “IEEE Standard Test Access Port and Boundary Scan Architecture,” IEEE, 1993. With the boundary-scan technique, all integrated circuit input and output pins comprise a scan cell in the signal path having a storage device and a switch. In normal operation, the switch connects the integrated circuit pins to the normal functional signals. In a test configuration, certain of the switches connect pins to the storage devices, allowing stored values to be applied to input pins, and the reading of output signals from storage devices connected to output pins. All scan cells are connected to a serial bus that provides for control of all input and output operations of the integrated circuit.
Boundary-scan design can be very effective for hardware testing, but is less so when applied to the testing of a system's diagnostic software. In high availability systems, diagnostic software is a critical system component used to identify problems and, in some cases, to attempt corrective actions. It is very important to be able to test and verify a system's diagnostic software. A common method of testing diagnostic software is to intentionally induce faults in the hardware while the system is in normal operating mode, see that the faults are properly identified by the diagnostic software and, where applicable, appropriate actions are taken. In many systems, it is possible to induce hardware faults through a system backplane by, for example, grounding backplane pins. In highly integrated systems, however, many nodes and circuits are hidden. Another problem with manually inducing faults through the grounding of accessible circuit nodes is that certain interface logic families, for example, the Advanced BiCMOS Technology (ABT) family of devices, have high drive capabilities that can overpower a manually induced short to ground.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a system to induce faults in highly integrated circuits. A further object of the present invention is to provide a system that is independent of the boundary scan technique. A further object of the present invention is to provide a system that does not require faults be induced through manually grounding or forcing high accessible circuit nodes.
The present invention is a system for fault insertion in an integrated circuit that resides in a functional portion of the integrated circuit. The fault insertion system is microprocessor controlled through a Fault Control Register (FCR). The FCR comprises two registers: a Fault Identification Register (FIR), and a Fault Apply Register (FAR). The FIR is connected to a FIR decode block which, depending on the values contained in the FIR, applies signals to one or more node fault logic blocks connected to nodes of the integrated circuit. The node fault logic blocks either apply a test signal to a circuit node, or apply the normal system signals to the node. The FAR controls an enable signal to the FIR decode block, and determines when, and the duration, that the test signal will be applied. An External Control Bit of the FAR also allows manual control of the test signal.


REFERENCES:
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B. Klenke, “Test Technology Overview Module 43,” RASSP Program, Pennsylvania State University, Aug. 30, 1998, Slide 85 of 173.

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