Integrated circuit fabrication process to reduce critical dimens

Details Integrated circuit fabrication process to reduce critical dimens Integrated circuit fabrication process to reduce critical dimens

1992-04-08

1993-11-09

Hearn, Brian E.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156643, 156651, 156652, H01L 21306

Patent

active

052599248

ABSTRACT:
A pad oxide is formed on a silicon substrate followed by a layer of polysilicon about 100 .ANG. thick. A silicon nitride layer is formed over said polysilicon layer then patterned with a first, fluorine-based, etch process to expose selected areas of the polysilicon layer. Then the exposed areas of polysilicon are removed using a second, chlorine-based, etch process fundamentally different from the first etch process. The high selectivity of the first etch process for nitride combined with the high selectivity of the second etch process for oxide, results in negligible CD loss in the overall process.

REFERENCES:
patent: 4490209 (1984-12-01), Hartman
patent: 4502915 (1985-03-01), Carter et al.
patent: 4541167 (1985-09-01), Havemann et al.
patent: 4568410 (1986-02-01), Thornquist
patent: 5087519 (1992-02-01), Teng

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