Integrated circuit devices providing improved short prevention

Details Integrated circuit devices providing improved short prevention Integrated circuit devices providing improved short prevention

2002-01-18

2004-01-20

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S387000, C438S270000, C438S271000

Reexamination Certificate

active

06680511

ABSTRACT:

RELATED APPLICATION
This application is related to Korean Application No. 2001-3066, filed Jan. 19, 2001, the disclosure of which is hereby incorporated herein by reference.
FIELD OF THE INVENTION
The present invention relates to integrated circuit devices and methods of fabricating the same and, more particularly, to integrated circuit devices having self aligned contacts and methods of fabricating the same.
BACKGROUND OF THE INVENTION
As integrated circuit devices decrease in size, the space available for wiring the device and a space between wirings within the device also decrease. For example, in order to form a contact that connects isolated device areas to each other through a highly conductive thin film, an aligning margin and a device isolation margin are typically utilized, thus a relatively large space is conducive to forming the integrated circuit device.
In a memory device, such as a Dynamic Random Access Memory (DRAM), the size of the contact is a factor used to determine the size of the memory cell. Recently, a manufacturing technique has been developed for manufacturing integrated circuit devices having a size of, for example, less than about 0.25 &mgr;m. It is typically difficult to form a fine contact using conventional fabrication methods. Furthermore, in memory devices having a plurality of conductive layers, the spacing between conductive layers is typically increased by the presence of an insulating layer interposed therebetween, thus possibly making it difficult to form the contact between the conductive layers. Therefore, in memory cells having a compact design and repeating patterns, self-aligned contacts are typically used to reduce the cell area.
A self-aligned contact is typically formed using step differences of peripheral structures. Various contacts may be obtained without using a mask by using the height of the peripheral structure, the thickness of an insulation film in a predetermined area where the contact is formed, and an etching method. A possible advantage of the self-aligned contact technique is that a fine contact can be formed without an aligning margin. A conventional self-aligned contact technique typically has a contact hole that is formed using an anisotropic etching process using an etching selectivity between an oxide film and a nitride film.
Now referring to
FIGS. 1A and 1B
, cross-sectional views of conventional integrated circuits having self-aligned contacts will be discussed below. Referring to
FIG. 1A
, a MOS transistor (not shown) is formed on an microelectronic substrate
10
having an active area defined by a field oxide film
12
. A first insulating layer
14
consisting of silicon oxide is formed by depositing silicon oxide on the surface of the microelectronic substrate
10
. A conductive layer for a bit line BL and a second insulating layer consisting of silicon nitride are deposited on the first insulating layer
14
. A photolithography process is carried out for patterning the second insulating layer and the conductive layer, so that bit line structures BL consisting of a second insulation film pattern
18
and a bit line
16
are formed. Silicon nitride is deposited on the surface of the resulting structure thereby forming a silicon nitride layer. The silicon nitride layer is anisotropically etched so as to form a spacer
20
consisting of silicon nitride on the sidewalls of the bit line structure BL.
Now referring to
FIG. 1B
, a third insulating layer
22
consisting of silicon oxide is formed by depositing silicon oxide on the surface of the resulting structure. A photoresist pattern (not shown) is formed in such a manner that a contact hole larger than the space between the bit line structures BL can be defined. The third insulating layer
22
is etched by an anisotropic etching process using the etching selectivity between a silicon oxide film and a silicon nitride film, thereby forming a storage node contact hole
24
for exposing a substrate area between the bit line structures BL. The photoresist pattern is used as an etching mask. A capacitor electrode (not shown) may be provided to bury the node contact hole
24
.
The silicon nitride film may be used as the spacer
20
, which is formed at the sidewall of the bit line structure BL, and the silicon oxide film may be used as the third insulating layer
22
. However, since the bond energy of the silicon oxide film may be greater than the bond energy of the silicon nitride film, it may be difficult to increase the etching selectivity between the silicon oxide film and the silicon nitride film as the size of the storage node contact hole
24
decreases.
Typically, a predetermined space is provided between the bit line structures BL, i.e. storage node contact hole
24
, by using the self-aligned contact process. If the width of the sidewall spacer
20
is reduced to increase the spacing, the sidewall spacer
20
may be consumed during the etching process for forming the self-aligned contact. Thus, a short may occur. Alternatively, if the width of the sidewall spacer
20
is increased, it may be difficult to bury a gap formed between the bit line structures BL as discussed above.
In addition, the sidewall spacer
20
, consisting of silicon nitride, typically has a dielectric constant above
7
. Thus, the parasitic capacitance between the bit lines may be twice the parasitic capacitance of the conventional contact structure in which the bit line is insulated from the storage electrode by using the silicon oxide film having the dielectric constant of 3.9.
Recently, to address the short comings of existing conventional structures, a method for forming the sidewall spacer in the contact hole after forming the self-aligned contact while preventing a short between the storage electrode and the bit line has been discussed. For example, this method is discussed in Japanese Patent No. JP9097880A2 entitled Semiconductor Storage Device and Its Manufacture to Hirosuke et al.
Now referring to
FIGS. 2A and 2B
, cross-sectional views of integrated circuits illustrating the method for manufacturing a DRAM cell disclosed in the above referenced Japanese Patent will be discussed. A field oxide film
52
is formed on a microelectronic substrate
50
by using a shallow trench isolation (STI) technique. A conventional MOS transistor manufacturing process is carried out so as to form a MOS transistor consisting of a gate region and a source/drain region on the surface of the substrate
50
.
Silicon oxide is deposited on the surface of the microelectronic substrate
50
forming a silicon oxide film
54
. A contact hole for exposing the source/drain region is formed by using a self-aligned contact process. A pad electrode
56
for burying the contact hole is formed at the same height as the gate. Silicon oxide is deposited on the surface of the resulting structure, thereby forming a first insulating layer
58
.
A conductive layer for a bit line, a second insulating layer consisting of silicon oxide, and a third insulating layer consisting of silicon nitride are sequentially formed on the first insulating layer
58
. The third insulating layer, the second insulating layer and the conductive layer are subject to a photolithography process, so that bit line structures BL consisting of a third insulating layer pattern
64
, a second insulating layer pattern
62
and a bit line
60
are formed.
Referring now to
FIG. 2B
, a fourth insulating layer
66
is formed by depositing silicon oxide on the resulting structure. The fourth insulating layer
66
is planarized by performing a chemical mechanical polishing (CMP) process. The third insulation pattern
64
may be used as a stopper.
Referring now to
FIG. 2C
, the fourth insulating layer
66
is etched using the high etching selectivity between the silicon oxide film and the silicon nitride film. The first insulating layer
58
formed on the pad electrode
56
is simultaneously etched so that a first insulating layer pattern
58
a
is formed. At the same time, a storage node contact hole
68
, which is self-aligned with respect to the bit

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