Static information storage and retrieval – Read/write circuit – Precharge
Reexamination Certificate
2003-07-10
2004-07-20
Auduong, Gene N. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Precharge
C365S063000
Reexamination Certificate
active
06765833
ABSTRACT:
RELATED APPLICATION
This application claims priority from Korean Patent Application No. 02-47380, filed Aug. 10, 2002, the contents of which are incorporated herein by reference in their entirety.
BACKGROUND OF THE INVENTION
The present invention relates to integrated circuit devices, and more particularly, to devices including equalization/precharge circuits for complementary data line pairs, such as complementary local and global input/output (I/O) line pairs found in memory circuits.
Dynamic random access memory (DRAM) circuits typically employ shared sense amplifiers to increase density, and include a hierarchical I/O line structure including local I/O line pairs and global I/O line pairs in order to simultaneously access multiple data.
Recently, as operating speeds of DRAMs have increased, signal transmission characteristics of a local I/O line pair and a global I/O line pair have become more critical, particularly signal transmission characteristics of local I/O line pairs. When write and read operations are not being performed, local I/O line pairs typically are equalized and precharged. When a write operation or a read operation is performed, equalization and precharge operations are typically suspended.
In order to improve signal transmission characteristics, the parasitic resistance and capacitance of the complementary lines of a local I/O line pair should be substantially the same. Otherwise, equalization and precharge of the local I/O line pair may occur asymmetrically, which can degrade signal transmission characteristics.
FIG. 1
is a diagram of the layout of a memory cell array portion of a conventional DRAM. Bit line sense amplifier blocks
11
a
-
11
d
are shared by upper memory cell blocks
13
a
-
13
d
and lower memory cell blocks
15
a
-
15
d
. A plurality of left local I/O line pairs LIO
0
_L/LIO
0
B_L, LIO
1
_L/LIO
1
B_L are connected to the bit line sense amplifier blocks
11
a
,
11
b
through a predetermined path (not shown) and are arranged in parallel. A plurality of right local I/O line pairs LIO
0
_R/LIO
0
B_R, LIO
1
_R/LIO
1
B_R are connected to the bit line sense amplifier blocks
11
c
,
11
d
through a predetermined path (not shown) and are arranged in parallel. For convenience of explanation, only two left local I/O line pairs and two right local I/O line pairs are shown in
FIG. 1
, but it will be appreciated that more I/O line pairs may be present.
The left local I/O line pairs LIO
0
_L/LIO
0
B_L, LIO
1
_L/LIO
1
B_L are not arranged in pairs. Rather, the left local I/O line pairs LIO
0
_L/LIO
0
B_L, LIO
1
_L/LIO
1
B_L are arranged in order of a first I/O line LIO
0
_L, a second I/O line LIO
1
_L, the complementary line LIO
0
B_L of the first I/O line and the complementary line LIO
01
B_L of the second I/O line. Likewise, the right local I/
0
line pairs LIO
0
_R/LIO
0
B_R, LIO
1
_R/LIO
1
B_R are not arranged in units of pair, but are arranged in order of a first I/O line LIO
0
_R, a second I/O line LIO
1
_R, the complementary line LIO
0
B_R of the first I/O line and the complementary line LIO
01
B_R of the second I/O line. In the regions A, B between respective bit line sense amplifiers are disposed equalization/precharge circuits which equalize and precharge the local I/O line pairs LIO
0
_L/LIO
0
B_L, LIO
1
_L/LIO
1
B_L, LIO
0
_R/LIO
0
B_R, LIO
1
_R/LIO
1
B_R.
FIG. 2
is a diagram of the structure of an equalization/precharge circuit in region A of FIG.
1
. Two equalization/precharge circuits
21
and
23
are arranged in region A. The equalization/precharge circuit
21
has a first equalization transistor
211
, a first precharge transistor
212
, a second precharge transistor
213
, a second equalization transistor
214
, a third precharge transistor
215
, and a fourth precharge transistor
216
. The equalization/precharge circuit
23
has a first equalization transistor
231
, a first precharge transistor
232
, a second precharge transistor
233
, a second equalization transistor
234
, a third precharge transistor
235
, and a fourth precharge transistor
236
. The first local I/O line pair LIO
0
, LIO
0
B is connected to a global I/O line pair GIOi, GIOiB through switch transistors SW
1
, SW
2
, and the second local I/O line pair LIO
1
, LIO
1
B are connected to a global I/O line pair GIOj, GIOjB.
FIG. 3
is a diagram of the structure of an equalization/precharge circuit in region B of FIG.
2
. Two equalization/precharge circuits
31
and
33
are arranged in the region B. The equalization/precharge circuit
31
has a first equalization transistor
311
, a second precharge transistor
312
, a third precharge transistor
313
, a second equalization transistor
314
, a third precharge transistor
315
, and a fourth precharge transistor
316
. The equalization/precharge circuit
33
has a first equalization transistor
331
, a second precharge transistor
332
, a third precharge transistor
333
, a second equalization transistor
334
, a third precharge transistor
335
, and a fourth precharge transistor
336
. The first left local I/O line pair LIO
0
_L, LIO
0
B_L is connected to a global I/O line pair GIOm, GIOmB through switch transistors SW
5
, SW
6
, and the second right local I/O line pair LIO
1
_R, LIO
1
B_R are connected to a global I/O line pair GIOn, GIOnB.
FIG. 4
is a diagram of a conventional layout for the equalization/precharge circuit shown in
FIG. 2
, and
FIG. 5
is a diagram of a conventional layout for the equalization/precharge circuit shown in FIG.
3
.
FIG. 6
is a diagram of an equivalent circuit that models parasitic resistance and parasitic capacitance in the layout of FIG.
4
. EQ
1
, PCH
1
, PCH
2
, EQ
2
, PCH
3
, and PCH
4
of
FIG. 4
correspond to the equalization transistor
231
, the precharge transistor
232
, the precharge transistor
233
, the equalization transistor
214
, the precharge transistor
215
, and the precharge transistor
216
, respectively, of FIG.
2
.
In the conventional layouts of
FIGS. 4 and 5
, an equalization/precharge circuit is arranged below local I/O line pairs LIO
0
/LIO
0
B, LIO
1
/LIO
1
B. Transistors are connected by using jumped lines, such as bitline poly silicon (bitline poly) or second metal (Metal
2
), which can make the parasitic resistance and capacitance of the local I/O lines LIO
0
, LIO
1
different from the parasitic resistance and capacitance of the complementary lines LIO
0
B, LIO
1
B, as shown in FIG.
6
. In particular, the parasitic capacitance CO
1
between LIO
0
and PCH
1
may be different from the parasitic capacitance C
01
b
between LIO
0
B and PCH
2
, and the parasitic resistance R
01
between LIO
0
and PCH
1
may be different from the parasitic resistance R
01
b
between LIO
0
B and PCH
2
. In addition, the parasitic capacitance C
02
between PCH
1
and EQ
1
may be different from the parasitic capacitance C
02
b
between PCH
2
and EQ
1
, and the parasitic resistance R
02
between PCH
1
and EQ
1
may be different from the parasitic resistance R
02
b
between PCH
2
and EQ
1
. The parasitic capacitance C
11
between LIO
1
and PCH
3
may be different from the parasitic capacitance C
11
b
between LIO
1
B and PCH
4
, and the parasitic resistance R
11
between LIO
1
and PCH
3
may be different from the parasitic resistance R
11
b
between LIO
1
B and PCH
4
. The parasitic capacitance C
12
between PCH
3
and EQ
2
may be different from the parasitic capacitance C
12
b
between PCH
4
and EQ
2
, and the parasitic resistance R
12
between PCH
3
and EQ
2
may be different from the parasitic resistance R
12
b
between PCH
4
and EQ
2
.
Due to these differences, equalization and precharge operations for the local I/O line LIO
0
and its complementary line LIOB may occur asymmetrically, and equalization and precharge operations for the local I/O line LIO
1
and its complementary line LIO
1
B may also occur asymmetrically. Consequently, signal transmission characteristics of the local I/O line pairs may be degraded, which may decrease operating speed.
SUMMARY OF THE INVENTION
According to some embodiments of the present invention, an integrated cir
Auduong Gene N.
Myers Bigel & Sibley & Sajovec
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