Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-06-30
2001-07-03
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S549000, C257S532000, C257S406000, C257S535000, C257S381000
Reexamination Certificate
active
06255697
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuit devices and methods of fabrication therefor, and more particularly, to integrated circuit devices with dummy conductive regions and methods of fabrication therefor.
BACKGROUND OF THE INVENTION
As the integration density of integrated circuit devices has increased, there is interest in developing techniques for forming isolation regions with reduced area. Trench isolation techniques are commonly used to reduce the area of the isolation region. In a typical trench isolation technique, a trench is etched into a semiconductor substrate, filled with an insulating film, and planarized by chemical mechanical polishing (CMP) to form a trench isolation region. Trench isolation techniques can form small isolation regions, as trenches can be made narrow and deep.
The area or density of the isolation regions in an integrated circuit may vary depending on location in the integrated circuit. For example, the density of active regions is typically lower in peripheral circuit regions than in memory cell array regions. Consequently, isolation regions in peripheral circuit areas typically occupy larger areas than isolation regions in a cell array region.
Relatively large trench isolation regions in peripheral circuit regions may be more subject to “dishing” during CMP, due to the relatively large trench size. In order to reduce dishing, fabrication techniques have been employed that reduce the total area of the isolation region. According to one technique, dummy active regions are formed at predetermined intervals in a large isolation region to reduce the size of the isolation region.
In forming gate lines for transistors in devices such as memory devices, a conductive layer typically is patterned by photolithography. The conductive layer preferably is patterned to achieve a more uniform distribution of conductive regions. Uniformity in the distribution of conductive regions can help ensure a uniform etch rate in longitudinal and latitudinal directions. Because gate lines in the chip may occur at irregular intervals, however, the conductive layer is patterned to form dummy gate lines along with the actual gate lines, particularly in regions having a relatively low gate line density.
Typically, these dummy gate lines are formed with little or no regard for their relationships to other structures in the substrate, such as the dummy active regions described above. Typically, at least a part of the dummy gate line overlaps a dummy active region. If a portion of a dummy active region is overlaid by a dummy gate line with a gate oxide film interposed therebetween, a floating capacitor may be formed. This floating capacitor may provide parasitic capacitance for another neighboring conductive region, e.g. a metal wiring region or a gate electrode. In the case of a dummy gate line lying adjacent an actual gate electrode, such parasitic capacitance may induce a voltage on the adjacent gate electrode that is sufficiently high to change the state of the transistor controlled by the gate electrode. This phenomenon may be particularly pronounced in highly-integrated semiconductor devices having line widths of 0.25 &mgr;m or less.
SUMMARY OF THE INVENTION
In light of the foregoing, it is an object of the present invention to provide integrated circuit devices and methods of fabrication therefor that can provide reduced dishing.
It is another object of the present invention to provide integrated circuit devices and methods of fabrication therefor that can provide dummy conductive structures with less floating capacitance.
These and other objects, features and advantages are provided according to the present invention by integrated circuit devices and fabrication methods therefor in which a plurality of dummy conductive regions are distributed in an area of a substrate and are constrained to overlie at least one isolation region that defines at least one dummy active region, i.e., such that the dummy conductive regions do not overlie the at least one dummy active region. The at least one isolation region may be formed, for example, by trench isolation or field oxide techniques. The dummy conductive regions may be formed, for example, from the same conductive layer used to form gate electrodes, capacitor electrodes, wiring patterns, or the like. In one embodiment according to the present invention, the at least one isolation region comprises a lattice-shaped isolation region defining an array of dummy active regions, and the plurality of dummy conductive regions comprises an array of dummy conductive regions disposed on node regions of the lattice-shaped isolation region. In another embodiment, the at least one isolation region includes an array of isolation regions that define a lattice-shaped dummy active region, and the plurality of dummy conductive regions comprises an array of dummy conductive regions disposed on the array of isolation regions.
When the at least one isolation region is formed by a trench isolation technique, distribution of the at least one isolation region in the form of a lattice or array interspersed among at least one dummy active region can help to reduce dishing in the formation of the at least one isolation region. Constraining dummy conductive regions to overlie the at least one isolation region can help reduce the creation of floating capacitances that can deleteriously affect device operation.
In particular, according to the present invention, an integrated circuit device is fabricated by forming at least one isolation region in an area of a semiconductor substrate, for example, a monolithic semiconductor substrate or a composite substrate such as a silicon on insulator (SOI) substrate. The at least one isolation region defines at least one active region. A plurality of dummy conductive regions is distributed in the area of the semiconductor substrate, with the dummy conductive regions being constrained to overlie the at least one isolation region. The dummy conductive regions may be formed, for example, from a conductive layer that is also used to form a gate electrode, a capacitor electrode or a wiring pattern. The dummy conductive regions may be formed on an insulation layer, e g., a gate insulation layer or an interlayer dielectric layer, that is formed on the substrate and covers the at least one isolation region and the at least one active region. Preferably, the dummy conductive regions are noncontiguous.
In one embodiment according to the present invention, a lattice-shaped isolation region is formed. The lattice-shaped isolation region includes an array of node regions linked by interconnecting regions, defining an array of dummy active regions. A plurality of dummy conductive regions are formed on the node regions of the lattice-shaped isolation region.
In another embodiment according to the present invention, an array of isolation regions is formed. The array of isolation regions defines a lattice-shaped dummy active region. An array of dummy conductive regions is formed on the array of isolation regions. A respective dummy conductive region may be formed on a respective one of the isolation regions of the array, or respective plurality dummy conductive regions may be formed on a respective one of the isolation regions of the array.
Related integrated circuit devices are also described.
REFERENCES:
patent: 5923969 (1999-07-01), Oyamatsu
patent: 6020616 (2000-02-01), Bothra et al.
patent: 6103592 (2000-08-01), Levy et al.
Jung Seok-kyun
Kim Young-Wug
Yoo Kwang-Dong
Meier Stephen D.
Mitchell James
Myers Bigel & Sibley & Sajovec
Samsung Electronics Co,. Ltd.
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