Integrated circuit devices having mode selection circuits...

Details Integrated circuit devices having mode selection circuits... Integrated circuit devices having mode selection circuits...

2000-02-01

2001-05-29

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S189110

Reexamination Certificate

active

06240030

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to the field of integrated circuit devices and, more particularly, to testing of integrated circuit devices.
BACKGROUND OF THE INVENTION
In general, burn-in stress testing or other predetermined testing operations may be performed on integrated circuit devices while they are still in the wafer state before final packaging. Unlike operations associated with a “normal” operating mode, test mode operations, such as burn-in stress testing or other predetermined testing operations, may be carried out using only a subset of all the input and output pins associated with an integrated circuit device.
Conventional integrated circuit devices may be designed to have an additional “dummy” pad through which a mode signal may be transmitted to place the integrated circuit device into a test mode (ie., configure the integrated circuit device for burn-in stress testing or other predetermined testing operations) or into a normal operating mode. The dummy pad may further include an input pin associated therewith for transmitting the mode signal. Unfortunately, because both the dummy pad and the input pin are typically assembled inside the chip, the chip size may increase. Furthermore, more complex test equipment may be needed to generate the mode signal, which may increase the manufacturing costs of such test equipment due to the additional complexity.
Consequently, there exists a need for improved integrated circuit devices having improved test capabilities.
SUMMARY OF THE INVENTION
Integrated circuit devices having improved test capabilities may include a mode selection circuit that generates a mode signal that designates an operational mode based on the magnitude of a mode control signal when a power supply signal transitions from a first state to a second state. The mode signal may be generated without the need for additional dummy pads and/or input pins, which may necessitate an increase in chip size and/or more complex test equipment to test an integrated circuit device.
More specifically, an embodiment of the present invention includes a preferred mode selection circuit that generates a mode signal that designates a first mode of the integrated circuit device when the power supply signal transitions from a first state to a second state while a magnitude of the mode control signal exceeds a potential threshold. Moreover, the mode selection circuit may also prevent subsequent changes in the magnitude of the mode control signal from disabling the first mode.
In accordance with an aspect of the present invention, the mode selection circuit may include a control circuit and an operation mode signal generator. The control circuit may include a level shifting circuit, a sequence detector circuit, and output logic connected in series. The level shifting circuit may generate an output signal by shifting the magnitude of the mode control signal downward. The sequence detector circuit is responsive to the output signal from the level shifting circuit and may generate an output signal in which the logic level is based on the relative sequencing of the voltage levels between the mode control signal and the power supply signal. The output logic is responsive to both the output signal from the sequence detector and the mode signal, and, preferably, generates a control circuit output signal by performing a logical NOR of these two signals.
In accordance with another aspect of the present invention, the operation mode signal generator may comprise a differential amplifier and a mode signal output circuit. The differential amplifier preferably has a first input terminal that is responsive to the mode control signal and a second input terminal that is responsive to the power supply signal. The mode signal output circuit may have an input terminal connected to an output terminal of the differential amplifier and generates the test-mode signal at an output terminal thereof in response to output signals from the differential amplifier and the control circuit.


REFERENCES:
patent: 5615159 (1997-03-01), Roohparvar
patent: 5646902 (1997-07-01), Park
patent: 5708604 (1998-01-01), Fontana et al.
patent: 5841691 (1998-11-01), Fink
patent: 1999-0057715 (1999-07-01), None

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