Integrated circuit devices having metastability protection...

Electronic digital logic circuitry – Signal sensitivity or transmission integrity

Reexamination Certificate

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Details

C326S026000, C327S198000

Reexamination Certificate

active

06184701

ABSTRACT:

RELATED APPLICATION
This application is related to Korean Application No. 98-19805, filed May 29, 1998, the disclosure of which is hereby incorporated herein by reference.
FIELD OF THE INVENTION
The present invention relates to integrated circuit devices, and more particularly to integrated circuit devices which may be prone to generating metastable output signals.
BACKGROUND OF THE INVENTION
Integrated circuit devices such as comparators, sense amplifiers, differential amplifiers and reference voltage generating circuits may be susceptible to generating output signals that are not always in logic 1 or 0 states. In particular, a differential amplifier which receives input signals at similar analog levels may be prone to generating an output signal in a metastable state (i.e., where the potential of the output signal is greater than a maximum logic 0 level (V
IL
) and less than a minimum logic 1 level (V
IH
)). Such generation of metastable outputs may result in device failure if devices that are responsive to the output signal interpret the state of the output signal incorrectly. Accordingly, there is a need to develop circuits having less susceptibility to metastable output generation.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide integrated circuit devices that have reduced susceptibility to metastable operation.
These and other objects, advantages and features of the present invention are provided by integrated circuit devices which include a main active circuit and a metastability detection/prevention circuit. The main active circuit may comprise a comparator, a sense amplifier, a differential amplifier or a voltage generating circuit, for example. The metastability detection/prevention circuit performs the function of detecting whether an output of the main active circuit has been disposed in a metastable state for a duration in excess of a transition duration. The output of the main active circuit may be considered as being in a metastable state if a potential of the output signal (V
POUT
) equals V
MS
, where V
MS
is in a range between V
IL
and V
IH
. If the output signal has been in a metastable state for a duration in excess of the transition duration, then the metastability detection/prevention circuit will generate a control signal at a designated logic level. This control signal is provided as an input to the main active circuit and causes the output of the main active circuit to be driven out of the metastable state (i.e., to a logic 1 or 0 level). In this manner, prolonged metastability can be prevented even if the values of the input signals to the main active circuit would otherwise dispose the output in a metastable state.


REFERENCES:
patent: 5081377 (1992-01-01), Freyman
patent: 5166561 (1992-11-01), Okura
patent: 5187385 (1993-02-01), Koike
patent: 5256914 (1993-10-01), Boomer
patent: 5754070 (1998-05-01), Baumann et al.
patent: 5789945 (1998-08-01), Cline
patent: 2-100414 (1990-04-01), None
Rabaey, “Digital Integrated Circuits: A Design Perspective”, Prentice Hall, 1996, pp. 334, 534-535.
Notice to Submit Response, Korean Application No. 10-1998-0019805, Jul. 31, 2000.

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