Integrated circuit device with stress reduction layer

Details Integrated circuit device with stress reduction layer Integrated circuit device with stress reduction layer

2009-04-08

2011-10-11

Pham, Hoai V (Department: 2892)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S632000, C257SE27060, C257SE27062

Reexamination Certificate

active

08035166

ABSTRACT:
An integrated circuit device is disclosed that includes a dual stress liner NMOS device having a tensile stress layer that overlies a NMOS gate film stack, a dual stress liner PMOS device having a compressive stress layer that overlies a PMOS gate film stack, a reduced-stress dual stress liner NMOS device having a stress reduction layer that extends between the tensile stress layer and the NMOS gate film stack, and a reduced-stress dual stress liner PMOS device having a stress reduction layer that extends between the compressive stress layer and the PMOS gate film stack. In embodiments of the invention additional reduced-stress dual stress liner NMOS devices and reduced-stress PMOS devices are formed by altering the thickness and/or the material properties of the stress reduction layer.

REFERENCES:
patent: 7214629 (2007-05-01), Luo et al.
patent: 7834399 (2010-11-01), Kanarsky et al.
patent: 2007/0040199 (2007-02-01), Kotani
patent: 2007/0262385 (2007-11-01), Nguyen et al.
patent: 2008/0003734 (2008-01-01), Chuang et al.
patent: 2008/0191284 (2008-08-01), Baiocco et al.
patent: 2009/0026548 (2009-01-01), Song et al.
patent: 2009/0057809 (2009-03-01), Richter et al.
patent: 2009/0079023 (2009-03-01), Berthold et al.
Ahmad, W.R.W et al., “TCAD Simulation of Local Mechanical Stress Reduction by Use of a Compressive Silicon Nitride/Silicon Oxynitride Etch Stop Bi-Layer for CMOS Performance Enhancement,”Proc. of the 31stInternational Conference on Electronics Manufacturing&Technology, Nov. 8-10, 2006, pp. 411-415, Kuala Lumpur, Malaysia.
Chen, X. et al., “Stress Proximity Technique for Performance Improvement with Dual Stress Liner at 45nm Technology and Beyond,”2006 Symposium on VLSI Technology Digest of Technical Papers, Jun. 13-15, 2006, pp. 60-61, Honolulu, Hawaii, USA.
Gehres, R. et al., “High Volume Manufacturing Ramp in 90nm Dual Stress Liner Technology,”Proc. of the 17thAnnual IEEE/SEMI Advanced Semiconductor Manufacturing Conference, May 22-24, 2006, pp. 411-416, Boston, Massachusetts, USA.

Affiliated with

Also associated with

Rating

Integrated circuit device with stress reduction layer does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Integrated circuit device with stress reduction layer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit device with stress reduction layer will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4286521