Integrated circuit device with MIM capacitance circuit and...

Details Integrated circuit device with MIM capacitance circuit and... Integrated circuit device with MIM capacitance circuit and...

2002-04-09

2003-10-28

Cao, Phat X. (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S238000, C438S239000, C438S240000, C438S241000, C257S300000, C257S303000

Reexamination Certificate

active

06638816

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an integrated circuit device having an MIM (Metal Insulator Metal) capacitance circuit, and a method of manufacturing such an integrated circuit device.
2. Description of the Related Art
Various capacitance circuits have been used to temporarily holding voltages. One of those various capacitance circuits is an MIM capacitance circuit, which is a minute capacitance circuit fabricated according to the thin film technology. The MIM capacitance circuit is of a structure including a lower metal electrode and an upper metal electrode that are disposed in facing relationship to each other with a capacitance film interposed therebetween.
One conventional circuit device having an MIM capacitance circuit and a transistor assembly will be described below with reference to
FIG. 1
of the accompanying drawings. As shown in
FIG. 1
, integrated circuit device
100
is of a hybrid structure including digital and analog circuits that are mounted on single p-type silicon substrate
101
.
The analog circuit has MIM capacitance circuit
102
as part thereof, and the digital circuit has CMOS transistor assembly
103
as part thereof. CMOS transistor assembly
103
comprises a pair of n-type and p-type MOS transistors
104
,
105
.
More specifically, element-separating field insulating film
106
is formed in the entire surface layer of silicon substrate
101
and has a pair of openings where there are disposed respective n-type MOS transistor
104
and p-type MOS transistor
105
.
At the positions of MOS transistors
104
,
105
, there are formed respective n well
110
a
and p well
110
b
in the surface layer of silicon substrate
101
. On both sides of the surface layers of n well
110
a
and p well
110
b,
there are formed n-type source and drain diffusion layers
111
a
and p-type source and drain diffusion layers
111
b,
respectively. Silicide layers
112
a,
112
b
containing titanium are formed in the respective surfaces of source and drain diffusion layers
111
a,
111
b,
and connected to respective aluminum electrodes
113
.
Gate insulating films
114
are formed respectively in n-type MOS transistor
104
and p-type MOS transistor
105
. Gate insulating films
114
extend from the surfaces of n well
110
a
and p well
110
b
to the surfaces of inner edges of source and drain diffusion layers
111
a,
111
b.
Gate layers
115
of polysilicon and gate electrodes
116
of tungsten silicide are deposited in the order named in the central regions of the surfaces of gate insulating films
114
.
Side walls
117
in the form of insulating films are formed outside of gate layers
115
and gate electrodes
116
. Aluminum electrodes
113
are connected to the respective surfaces of gate electrodes
116
. CMOS transistor
103
of the above structure is covered in its entirety with interlayer insulating film
118
which has contact holes where aluminum electrodes
113
are buried.
MIM capacitance circuit
102
is formed on the surface of field insulating film
106
and has lower metal electrode
120
disposed on the surface of field insulating film
106
, insulating capacitance film
121
disposed on lower metal electrode
120
, and upper metal electrode
122
disposed as a second conductive layer on insulating capacitance film
121
. Lower metal electrode
120
comprises polysilicon film
123
and tungsten silicide film
124
as a first conductive layer. Side walls
125
are formed outside of lower metal electrode
120
, insulating capacitance film
121
, and upper metal electrode
122
.
Insulating capacitance film
121
is formed of HTO (High Temperature Oxide), and upper metal electrode
122
is formed of tungsten silicide. As shown in
FIG. 5
of the accompanying drawings, insulating capacitance film
121
and upper metal electrode
122
are patterned in an area smaller than the area of lower metal electrode
120
, and side walls
125
are formed outside of insulating capacitance film
121
and upper metal electrode
122
.
Aluminum electrode
113
is connected to the surface of upper metal electrode
122
. Aluminum electrode
113
is also connected to a region of the surface of lower metal electrode
120
which extends outwardly of insulating capacitance film
121
and upper metal electrode
122
.
In
FIG. 1
, MOS transistors
104
,
105
and MIM capacitance circuit
102
are shown as having equal dimensions. Actually, however, MIM capacitance circuit
102
has an area that is sufficiently larger than the areas of MOS transistors
104
,
105
.
With integrated circuit device
100
of the structure described above, CMOS transistor
103
can contribute to the digital processing of the digital circuit, and MIM capacitance circuit
102
can hold a variable voltage as an analog value of the analog circuit.
A process of fabricating integrated circuit device
100
will be described below with reference to
FIGS. 2
a
through
4
b
of the accompanying drawings. First, as shown in
FIG. 2
a,
an impurity of boron or phosphor is introduced into the surface layer of p-type silicon substrate
101
by way of ion implantation to form n well
110
a
and p well
110
b
therein, and then field insulating film
106
is formed on the surface of silicon substrate
101
in a predetermined pattern which allows portions of the surfaces of n well
110
a
and p well
110
b
to be exposed.
Thereafter, as shown in
FIG. 2
b,
gate insulating film
114
is formed by way of thermal oxidization on the exposed surfaces of n well
111
a
and p well
110
b.
As shown in
FIG. 3
a,
polysilicon layer
130
, tungsten silicide layer
131
as a first conductive layer, HTO layer
132
, and tungsten silicide layer
133
are grown in the order named on the entire surface of silicon substrate
101
. At this time, polysilicon layer
130
and tungsten silicide layers
131
,
133
are formed according to a sputtering process or a CVD process, and HTO layer
132
is formed according to a CVD process.
Then, as shown in
FIG. 3
b,
resist mask
134
having a predetermined pattern is deposited on the surface of upper tungsten silicide layer
133
, and the assembly with resist mask
134
is etched by way of dry etching to pattern tungsten silicide layer
133
and HTO layer
132
, thus forming insulating capacitance film
121
and upper metal electrode
122
of MIM capacitance circuit
102
.
Thereafter, as shown in
FIG. 4
a,
resist mask
135
having a predetermined pattern is deposited on the surface of lower tungsten silicide layer
131
which has been exposed by the above patterning process. The assembly with the resist mask
135
is etched by way of dry etching to pattern tungsten silicide layer
131
and polysilicon layer
130
, thus forming lower metal electrode
120
of MIM capacitance circuit
102
and gate electrodes
116
and gate layers
115
of MOS transistors
104
,
105
.
The above dry etching process employs etching gases of CHF
3
/O
2
, CF
4
, etc. Resist masks
134
,
135
are removed by an ammonia-based solution after the dry etching process.
Then, as shown in
FIG. 4
b,
after an HTO layer (not shown) is formed on the entire surface of silicon substrate
101
from which resist masks
134
,
135
have been removed, it is etched back to form side walls
117
of MOS transistors
104
,
105
and sidewalls
125
of MIM capacitance circuit
102
. After side walls
117
,
125
have been formed, thin oxide film
136
which will serve as an ion implantation mask is deposited on the entire surface of the assembly.
Then, a p-type impurity is introduced by way of ion implantation from above the surface of thin oxide film
136
into the position of n well
110
a
of MOS transistor
104
, and an n-type impurity is introduced by way of ion implantation from above the surface of thin oxide film
136
into the position of p well
110
b
of MOS transistor
105
. These introduced impurities are then activated by annealing to form source and drain diffusion layers
111
a,
111
b.
Then, thin oxide film
136
is removed by dry etching, exposing source an

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