Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Flip chip
Reexamination Certificate
2001-11-08
2003-07-01
Cuneo, Kamand (Department: 2829)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Flip chip
C257S734000, C257S737000, C174S257000, C174S260000
Reexamination Certificate
active
06586843
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to integrated circuit devices. It particularly relates to a method and apparatus for improving bump formation in flip chip assemblies.
2. Background
In recent years, the usage of Flip-Chip technology has grown in electronics manufacturing. Flip-Chip is a process by which an integrated circuit (IC) is mounted on a substrate (e.g., ceramic, epoxy, etc.), and attached with electrically conductive (e.g., metallic) bumps. The unique aspect of such a chip is that it is mounted “upside-down”, with the active side down. The IC is commonly soldered on to the substrate by thermocompression or heat-welding, and this process is commonly used on printed circuit boards (PCB) for small numbers of connections, in electronic products which must be very highly miniaturized.
Compared to traditional wire bonding interconnection, flip-chip technology offers tremendous advantages such as eliminating the need for wire bond connections, increasing input/output (I/O) density, and using less space on PCBs. By replacing a finite number of perimeter lead wires with an almost unlimited number of solder bumps between the chip and the substrate, flip-chip technology achieves higher I/O counts and faster operating speeds than wire bonding. Other advantages of flip-chip technology include eliminating conventional packaging to meet demanding high-speed electrical requirements while providing a true chip-scale form factor, and shortening electrical paths so unwanted effects such as inductance and noise are greatly reduced. Additionally, flip-chip technology allows higher-density packaging (e.g., 16 Die on DIMM—Dual In-Line Memory Module as FCOB—Flip Chip on Board vs. 8 Die on DIMM in BGA-Ball Gird Array format) and provides very good thermal applications in most applications.
FIG. 1
shows the typical process
100
followed in manufacturing flip-chip assemblies (devices). At step
105
, a bumped-die (e.g. solder-bumped) is dipped into a thin film of flux. At step
110
, the bumped-die is attached facedown on to a PCB (substrate). The solder provides mechanical, thermal, and electrical connections to the PCB. Preceding this step, there may be an alignment step where the bumps are aligned over the bond pads of the substrate. At step
115
, solder reflow is applied to the device (assembly) to help stabilize the bump attachment (solder joints). At step
120
, underfill material is applied between the flip chip and substrate along one or two edges of the die to minimize stress-induced failure of the solder interconnects. The underfill material is allowed to flow, by capillary action, between the device and the PCB through a small gap (e.g., typically less than 0.003 inches). At step
125
, after the adhesive has completely underfilled the die, a fillet of the material is applied along the remaining edges of the chip to help reduce peripheral stress concentrations. Prior to the underfill application, the substrate may be preheated to very high temperatures (e.g., 80 to 100 degrees Celsius) to improve the flow characteristics of the underfill and reduce the risk of air voids ensuring a moisture-free substrate. Thereafter, at step
130
, the underfill may be cured in an oven at elevated temperature (e.g., 150-170 degrees Celsius) over an extended period of time (e.g., 1-1.5 hours) to form void-free bonds that increase the thermal efficiency of the device and help reduce stress on the chip.
In flip-chip processing, the underfill materials are essential to flip-chip reliability by reducing and redistributing stresses and strains on the flip chip by minimizing coefficient of thermal expansion (CTE) mismatch among the chip, circuit board, and solder joints. Also, underfill materials improve thermal management of flip-chip devices by allowing rapid dissipation of heat through the back of the die.
However, despite the presence of the underfill materials, there still exists CTE mismatches, including physical and mechanical property mismatches, among the different materials forming the flip-chip device (e.g., lead, epoxy, ceramic, etc.) which leads to bump fatigue (e.g., formation of cracks) and premature device failure as the device goes through thermal cycling during operation. Therefore, to provide increased compliancy bumps that prevent premature device failure and reduce bump fatigue, there is a need to form bumps that adhesively bond to the substrate contact pads to form true covalently bonded devices with uniform mechanical and physical properties that lengthen flip-chip device operational life.
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Chen Tim
Sterrett Terry
Cuneo Kamand
Geyer Scott B
Intel Corporation
Kenyon & Kenyon
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