Integrated circuit device isolating methods including silicon sp

Details Integrated circuit device isolating methods including silicon sp Integrated circuit device isolating methods including silicon sp

1997-04-14

1998-10-20

Dang, Trung

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Recessed oxide by localized oxidation

438439, 438445, 438444, H01L 2176

Patent

active

058245944

ABSTRACT:
An integrated circuit device is isolated by forming a pad oxide layer on an integrated circuit substrate. A mask pattern is formed on the pad layer. The mask pattern includes sidewalls which selectively expose the pad oxide layer between the sidewalls. A silicon spacer is formed on the sidewalls. An oxidation barrier film is formed on the silicon spacer and on the exposed pad oxide layer. The integrated circuit substrate is then oxidized through the oxidation barrier film to form a device isolating layer. The oxidation barrier film on the exposed pad oxide layer is thinner than the oxidation barrier film on the sidewalls. Thus, oxidation of the silicon spacer is delayed relative to the substrate.

REFERENCES:
patent: 5457067 (1995-10-01), Han
patent: 5512509 (1996-04-01), Han
patent: 5629230 (1997-05-01), Fazan et al.
patent: 5658822 (1997-08-01), Wu et al.
Ahn et al., "A Highly Practice Modified LOCOS Isolation Technology for the 256 Mbit DRAM", IEDM Technical Digest, International Electron Devices Meeting 1994, Dec. 11-14, 1994, pp. 679-682.

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