Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Configuration or pattern of bonds
Reexamination Certificate
2003-07-03
2004-12-28
Clark, Jasmine (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Configuration or pattern of bonds
C257S691000, C257S202000, C257S203000
Reexamination Certificate
active
06836026
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
This invention relates to integrated circuits, and more particularly to input output cell designs for both input output limited integrated circuits and core limited integrated circuits.
2. Description of Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
Integrated circuits such as application specific integrated circuits (ASICs) and application specific standard products (ASSPs) can be categorized as either input output (I/O) limited integrated circuits (ICs) or core limited ICs. For I/O limited designs, the number of I/O cells dictates the size of the die. In this scenario, it is generally desirable to use tall but narrow I/O cells to minimize the die size. For example, current approaches for I/O limited IC designs include placing the I/O cells around the periphery of the die. Therefore, the total chip size is driven by the width of the I/O cells. As a result, I/O cells should ideally be as narrow as possible. However, a fixed silicon area is required for the I/O circuit structures. Consequently, the I/O cell height is increased to accommodate the decrease in width.
For core limited designs, the size of the core logic region dictates the die size. In this scenario, short but wide I/O cells free more area on the die for core logic. For example, current approaches for core limited IC designs include placing I/O cells around the periphery of the die. However, the total chip size is driven by the size of the core logic area. Therefore, for a given total chip size, making I/O cells as short as possible increases the area provided for core logic. As a result, I/O cells should ideally be as short as possible. However, a fixed silicon area is required for the I/O circuit structures. Consequently, the I/O cell width is increased to accommodate the decrease in height.
Creating a combined I/O and core limited solution, therefore, presents a problem since I/O cells that are narrow and tall benefit I/O limited designs, but I/O cells that are short and wide benefit core limited designs. To address both I/O and core limited designs, I/O circuit and chip designers use one or more of the following approaches. For example, I/O cell developers may compromise the aspect ratio of the I/O cell by creating an I/O cell that is not as narrow as possible and not as short as possible thereby creating a tradeoff between the two extremes. Alternatively, I/O cell developers may create two separate physical layouts, one for each I/O type of device. One layout may include narrow but tall I/O cells that are optimized for I/O limited designs. The other layout may include short but wide I/O cells that are optimized for core limited designs.
There are, however, several disadvantages to the current approaches for addressing both types of limited designs. For example, when the I/O cell aspect ratio is compromised, neither I/O limited nor core limited designs are fully optimized. In particular, for an I/O limited IC, a wider than necessary I/O cell will increase the I/O limited die size even though the core area of the chip is underutilized. For a core limited IC, a taller than required I/O cell will decrease the available core area in the core limited design even though some sections of the I/O region are underutilized. In another example, compromising the I/O cell aspect ratio requires careful consideration by the I/O circuit designer to ensure that I/O and/or core limited designs are not over-penalized.
In such an approach, a breakdown of projected I/O and core limited designs and actual die sizes is estimated as well as projections for manufacturing volumes and revenues for each design over the life of the semiconductor technology. Incorrect assessment of this tradeoff becomes difficult to correct once I/O libraries are released. Furthermore, due to the complexity of the aspect ratio assessment, the overall I/O library development time is increased. Moreover, in many cases, projected die sizes, volumes, and revenues are nearly impossible to predict, and as a result, non-ideal solutions may be deployed. The non-ideal solutions are accepted and used at the expense of increased total chip size and die cost.
Creating separate layouts is an alternative solution that addresses both I/O and core limited applications. However, developing and maintaining separate I/O layouts requires more effort from circuit designers. Additionally, the timing and performance characteristics of each layout version must be identical such that they can be used interchangeably on a semiconductor design, which impacts the chip level operation. In addition, exclusive use of either I/O or core limited cell versions may cause a design that is originally I/O limited to become core limited or vice versa. As a result, semiconductor applications will require the combined use of both I/O and core limited I/O layout versions to ensure that the total chip size is optimized. The chip designer must, therefore, switch I/O or core limited I/O layout versions on an I/O cell specific basis until the optimum die size is reached. These iterations increase the design complexity and the design time.
Accordingly, it may be desirable to provide an I/O cell layout and I/O cell aspect ratio that is optimal for both I/O and core limited designs thereby decreasing die waste area and die cost and eliminating the compromise between the I/O aspect ratio currently used to balance the I/O and core limited designs.
SUMMARY OF THE INVENTION
The problems outlined above may be in large part addressed by an integrated circuit (IC) that includes bonding pads and an input output (I/O) region surrounding a core region. The I/O region includes I/O cells. A width of the I/O cells is approximately equal to or less than a width of the bonding pads. In this manner, the I/O cells may be designed as I/O cells of an I/O limited IC. In addition, an aspect ratio of the I/O cells may be greater than about 2. Furthermore, a height of the I/O cells may be approximately equal to an area sufficient for components of the I/O cells divided by the width.
This I/O limited IC design, however, may be easily modified for a core limited IC. For example, core logic may be arranged within the I/O region. In this manner, an I/O limited IC design may be modified to accommodate a core limited IC without modifying the I/O cells (i.e., the dimensions of the I/O cells may be the same for an I/O limited IC design and a core limited IC design). Instead, space within the I/O region originally allocated for I/O cells in the I/O limited IC design may be reallocated for core logic to accommodate a core limited IC.
In one embodiment, the I/O cells may be arranged into continuous groups with space between the continuous groups for the core logic. In another embodiment, the core logic may occupy a continuous area of the I/O region equal to or greater than an area of at least two of the I/O cells. The core logic may also be arranged into more than one core logic areas within the I/O region. In some embodiments, the core logic may extend from the core region beyond an outermost boundary of the I/O region. A width of the core logic may be less than a width of the core region.
In an additional embodiment, the I/O region may include 4 I/O sub-regions. Each of the 4 I/O sub-regions may be arranged proximate a different side of the core region. A portion of each of the 4 I/O sub-regions may include core logic. In addition, the I/O cells may be arranged on each side of the core region. In some embodiments, the bonding pads may be arranged in one row spaced from the I/O region. In a different embodiment, the bonding pads may be arranged in first and second rows. The second row may be spaced farther from the I/O region than the first row. The integrated circuit may be further configured as described herein.
Another embodiment relates to an IC that includes 4 groups of bonding pads. Each of the groups of bonding pads is arranged along an axis parallel to a different side of a core region. This
Ali Anwar
Lau Tauman T.
Young Max M.
Clark Jasmine
Conley & Rose, P.C.
LSI Logic Corporation
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